[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2] arm/vgic-v2: Fix undefined behavior in vgic_fetch_itargetsr()


  • To: Jahan Murudi <jahan.murudi.zg@xxxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • From: "Orzel, Michal" <michal.orzel@xxxxxxx>
  • Date: Mon, 2 Jun 2025 08:54:06 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xBAgPyn6HzTm/4YpoVVOEcj5/JuxWsqz64rHlPDUomY=; b=DSh/upPBQj6iF94N5u1hzRmn2+bh0A8wktKb/QW9HV7/2VBVyz7dQl0QRCe9vECq60UZtlDYFmGWEQ4QTBeNW1f7vdGObmno4E+W5oSGN8BProfkwzcK64SZTR8nxIVwbpH6H4vw7d+OTDsNC7TRmC37oJDxAcPuhEwie0lKG88bJP3Ty6W+jwgQTsC/VKhOqZoLI+fwBTT8+V7eFLtCD1zOx0kr3Eo86jX4H1vD6XVJPi5TaCPvScfFxs7jdWRlIEgv8odqvHEGElotVCdZqzenPpZqT+caP6oOzebYrw2TL5y8hHHpWiEovZF+op2tpUuDLEzWBe6V7kmmjJL1dQ==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=W9xFAWaBzy0hhzVacfDY9G1vxWyDLALYxTznFaSYOrVNba+jpUq347cwlUEiIvw+8iQT3nO7mCy/NEM999MBVygidQdkKFuuK5KXyCGrx5VUOsEEDcg94x+4kKaiU0xjLXm1LCzvKuBg78lNNsDP88u+wklM+aC860WeaH722LZ/TqiA4YriYAqCYTVztN5hBNRTN+PHFGsqSge33Hy79OPBg1K78ODEo2SPi9BifVRM1atIDxadKrDf75fAjOCZzmPKRdwfUBjelvNBcBBYkXlMRBT2CMVcSRBzfV/Q7FWN+0/YeAUxK4cCi4PCy0VTxLC5JzWPGDTwuQuI9RFKUg==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
  • Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
  • Delivery-date: Mon, 02 Jun 2025 06:54:21 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>


On 01/06/2025 18:32, Jahan Murudi wrote:
> The current implementation performs left shift operations that may trigger
> undefined behavior when the target value is too large. This patch:
> 
> 1. Changes the shift from signed (1) to unsigned (1U) to ensure well-defined
NIT for the future: Use imperative mood

>    behavior for all valid target values
> 2. Maintains identical functionality while fixing the UBSAN warning
> 
> The issue was detected by UBSAN:
> (XEN) UBSAN: Undefined behaviour in arch/arm/vgic-v2.c:73:56
> (XEN) left shift of 128 by 24 places cannot be represented in type 'int'
> (XEN) Xen WARN at common/ubsan/ubsan.c:174
> 
> Signed-off-by: Jahan Murudi <jahan.murudi.zg@xxxxxxxxxxx>
Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>

~Michal

> 
> ---
> Changed since v1:
>  * Added space after subject line
> ---
>  xen/arch/arm/vgic-v2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
> index a19d610178..642407fd5b 100644
> --- a/xen/arch/arm/vgic-v2.c
> +++ b/xen/arch/arm/vgic-v2.c
> @@ -70,7 +70,7 @@ static uint32_t vgic_fetch_itargetsr(struct vgic_irq_rank 
> *rank,
>      offset &= ~(NR_TARGETS_PER_ITARGETSR - 1);
>  
>      for ( i = 0; i < NR_TARGETS_PER_ITARGETSR; i++, offset++ )
> -        reg |= (1 << read_atomic(&rank->vcpu[offset])) << (i * 
> NR_BITS_PER_TARGET);
> +        reg |= (1U << read_atomic(&rank->vcpu[offset])) << (i * 
> NR_BITS_PER_TARGET);
>  
>      return reg;
>  }




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.