Re: [PATCH v3 02/14] xen/riscv: introduce support of Svpbmt extension and make it mandatory

[Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>]

On 5/22/25 9:26 AM, Jan Beulich wrote:

> On 21.05.2025 18:03, Oleksii Kurochko wrote:
> > Svpbmt extension is necessary for chaning the memory type for a page contains
> > a combination of attributes that indicate the cacheability, idempotency,
> > and ordering properties for access to that page.
> >
> > As a part of the patch the following is introduced:
> > - Svpbmt memory type defintions: PTE_PBMT_{NOCACHE,IO}.
> > - PAGE_HYPERVISOR_{NOCACHE,WC}.
> > - RISCV_ISA_EXT_svpbmt and add a check in runtime that Svpbmt is
> >   supported by platform.
> > - Update riscv/booting.txt with information about Svpbmt.
> > - Update logic of pt_update_entry() to take into account PBMT bits.
> >
> > Use 'unsigned long' for pte_attr_t as PMBT bits are 61 and 62 and it doesn't
> > fit into 'unsigned int'. Also, update function prototypes which uses
> > 'unsigned int' for flags/attibutes.
> >
> > Enable Svpbmt for testing in QEMU as Svpmbt is now mandatory for
> > Xen work.
> >
> > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
> >       
> Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
>
>     
Thanks.

I just noticed a minor typo (PMBT_{IO,NOCACHE}->PMBT_{IO,NOCACHE} in the changes:

xen$ git diff
diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h
index 81b91b63d8..4cb0179648 100644
--- a/xen/arch/riscv/include/asm/page.h
+++ b/xen/arch/riscv/include/asm/page.h
@@ -45,8 +45,8 @@
  *  10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
  *  11 - Rsvd   Reserved for future standard use
  */
-#define PTE_PMBT_NOCACHE            BIT(61, UL)
-#define PTE_PMBT_IO                 BIT(62, UL)
+#define PTE_PBMT_NOCACHE            BIT(61, UL)
+#define PTE_PBMT_IO                 BIT(62, UL)
 
 #define PTE_LEAF_DEFAULT            (PTE_VALID | PTE_READABLE | PTE_WRITABLE)
 #define PTE_TABLE                   (PTE_VALID)
@@ -59,12 +59,12 @@
 /*
  * PAGE_HYPERVISOR_NOCACHE is used for ioremap().
  *
- * Both PTE_PMBT_IO and PTE_PMBT_NOCACHE are non-cacheable, but the difference
+ * Both PTE_PBMT_IO and PTE_PBMT_NOCACHE are non-cacheable, but the difference
  * is that IO is non-idempotent and strongly ordered, which makes it a good
  * candidate for mapping IOMEM.
  */
-#define PAGE_HYPERVISOR_NOCACHE     (PAGE_HYPERVISOR_RW | PTE_PMBT_IO)
-#define PAGE_HYPERVISOR_WC          (PAGE_HYPERVISOR_RW | PTE_PMBT_NOCACHE)
+#define PAGE_HYPERVISOR_NOCACHE     (PAGE_HYPERVISOR_RW | PTE_PBMT_IO)
+#define PAGE_HYPERVISOR_WC          (PAGE_HYPERVISOR_RW | PTE_PBMT_NOCACHE)
 
 /*
  * The PTE format does not contain the following bits within itself;
@@ -77,7 +77,7 @@
 
 #define PTE_ACCESS_MASK (PTE_READABLE | PTE_WRITABLE | PTE_EXECUTABLE)
 
-#define PTE_PBMT_MASK   (PTE_PMBT_NOCACHE | PTE_PMBT_IO)
+#define PTE_PBMT_MASK   (PTE_PBMT_NOCACHE | PTE_PBMT_IO)
 
 /* Calculate the offsets into the pagetables for a given VA */
 #define pt_linear_offset(lvl, va)   ((va) >> XEN_PT_LEVEL_SHIFT(lvl))

I will send them as a part of v4. (if it can't
be done during commit)

~ Oleksii