Re: [PATCH v4 6/7] arm/mpu: Provide a constructor for pr_t type

[Luca Fancellu <Luca.Fancellu@xxxxxxx>]

Hi Ayan,

>> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
>> index 40ccf99adc94..2e0aeb486ff8 100644
>> --- a/xen/arch/arm/mpu/mm.c
>> +++ b/xen/arch/arm/mpu/mm.c
>> @@ -9,6 +9,7 @@
>>  #include <xen/types.h>
>>  #include <asm/mpu.h>
>>  #include <asm/mpu/mm.h>
>> +#include <asm/page.h>
>>  #include <asm/sysregs.h>
>> 
>>  struct page_info *frame_table;
>> @@ -151,6 +152,73 @@ void write_protection_region(const pr_t *pr_write, 
>> uint8_t sel)
>>          BUG(); /* Can't happen */
>>      }
>>  }
>> +
>> +pr_t pr_of_xenaddr(paddr_t base, paddr_t limit, unsigned int attr_idx)
>> +{
>> +    prbar_t prbar;
>> +    prlar_t prlar;
>> +    pr_t region;
>> +
>> +    /* Build up value for PRBAR_EL2. */
>> +    prbar = (prbar_t) {
>> +        .reg = {
>> +            .ap = AP_RW_EL2,      /* Read/Write at EL2, no access at 
>> EL1/EL0. */
>> +            .xn = PRBAR_EL2_XN_ENABLED,   /* No need to execute outside 
>> .text */
>> +        }};
>> +
>> +    switch ( attr_idx )
>> +    {
>> +    case MT_NORMAL_NC:
>> +        /*
>> +         * ARM ARM: Overlaying the shareability attribute (DDI
>> +         * 0406C.b B3-1376 to 1377)
>> +         *
>> +         * A memory region with a resultant memory type attribute of normal,
>> +         * and a resultant cacheability attribute of Inner non-cacheable,
>> +         * outer non-cacheable, must have a resultant shareability attribute
>> +         * of outer shareable, otherwise shareability is UNPREDICTABLE.
>> +         *
>> +         * On ARMv8 sharability is ignored and explicitly treated as outer
>> +         * shareable for normal inner non-cacheable, outer non-cacheable.
>> +         */
>> +        prbar.reg.sh = LPAE_SH_OUTER;
>> +        break;
>> +    case MT_DEVICE_nGnRnE:
>> +    case MT_DEVICE_nGnRE:
>> +        /*
>> +         * Shareability is ignored for non-normal memory, Outer is as
>> +         * good as anything.
>> +         *
>> +         * On ARMv8 sharability is ignored and explicitly treated as outer
>> +         * shareable for any device memory type.
>> +         */
>> +        prbar.reg.sh = LPAE_SH_OUTER;
>> +        break;
>> +    default:
>> +        /* Xen mappings are SMP coherent */
>> +        prbar.reg.sh = LPAE_SH_INNER;
>> +    }
>> +
>> +    /* Build up value for PRLAR_EL2. */
>> +    prlar = (prlar_t) {
>> +        .reg = {
> #ifdef CONFIG_ARM_64
>> +            .ns = 0,        /* Hyp mode is in secure world */
> #endif

yes this part will be introduced by you together with the pr_t definition,
in this patch the overall pr_of_xenaddr is protected by CONFIG_ARM_64

Cheers,
Luca