[PATCH v4 04/15] x86/msr: Rename rdpmcl() to rdpmc()

["Xin Li (Intel)" <xin@xxxxxxxxx>]

Now that rdpmc() is gone, i.e. rdpmcl() is the sole PMC read helper,
simply rename rdpmcl() to rdpmc().

Signed-off-by: Xin Li (Intel) <xin@xxxxxxxxx>
Acked-by: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>
Acked-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
---

Changes in v3:
*) Explain the reason of the renaming in the changelog (Dave Hansen).
*) Use shorter name rdpmc() instead of rdpmcq() as the name of the
   sole PMC read helper (Sean Christopherson).
---
 arch/x86/events/amd/uncore.c              |  2 +-
 arch/x86/events/core.c                    |  2 +-
 arch/x86/events/intel/core.c              |  4 ++--
 arch/x86/events/intel/ds.c                |  2 +-
 arch/x86/include/asm/msr.h                |  2 +-
 arch/x86/include/asm/paravirt.h           |  2 +-
 arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 ++++++------
 7 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 2a3259df619a..42c833cf9d98 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -108,7 +108,7 @@ static void amd_uncore_read(struct perf_event *event)
        if (hwc->event_base_rdpmc < 0)
                rdmsrq(hwc->event_base, new);
        else
-               rdpmcl(hwc->event_base_rdpmc, new);
+               rdpmc(hwc->event_base_rdpmc, new);
 
        local64_set(&hwc->prev_count, new);
        delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 85b55c1dc162..ea618dd8a678 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -134,7 +134,7 @@ u64 x86_perf_event_update(struct perf_event *event)
         */
        prev_raw_count = local64_read(&hwc->prev_count);
        do {
-               rdpmcl(hwc->event_base_rdpmc, new_raw_count);
+               rdpmc(hwc->event_base_rdpmc, new_raw_count);
        } while (!local64_try_cmpxchg(&hwc->prev_count,
                                      &prev_raw_count, new_raw_count));
 
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 394fa83b537b..8ac7a03ae4e9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2724,12 +2724,12 @@ static u64 intel_update_topdown_event(struct perf_event 
*event, int metric_end,
 
        if (!val) {
                /* read Fixed counter 3 */
-               rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
+               rdpmc((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
                if (!slots)
                        return 0;
 
                /* read PERF_METRICS */
-               rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
+               rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
        } else {
                slots = val[0];
                metrics = val[1];
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 410a8975d1b9..be05e93b48e7 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2274,7 +2274,7 @@ intel_pmu_save_and_restart_reload(struct perf_event 
*event, int count)
        WARN_ON(this_cpu_read(cpu_hw_events.enabled));
 
        prev_raw_count = local64_read(&hwc->prev_count);
-       rdpmcl(hwc->event_base_rdpmc, new_raw_count);
+       rdpmc(hwc->event_base_rdpmc, new_raw_count);
        local64_set(&hwc->prev_count, new_raw_count);
 
        /*
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index e05466e486fc..ae96d35e0621 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -234,7 +234,7 @@ static inline int rdmsrq_safe(u32 msr, u64 *p)
        return err;
 }
 
-#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
+#define rdpmc(counter, val) ((val) = native_read_pmc(counter))
 
 #endif /* !CONFIG_PARAVIRT_XXL */
 
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index c4dedb984735..faa0713553b1 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -244,7 +244,7 @@ static inline u64 paravirt_read_pmc(int counter)
        return PVOP_CALL1(u64, cpu.read_pmc, counter);
 }
 
-#define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
+#define rdpmc(counter, val) ((val) = paravirt_read_pmc(counter))
 
 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned 
entries)
 {
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c 
b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index 26c354bdea07..15ff62d83bd8 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -1019,8 +1019,8 @@ static int measure_residency_fn(struct perf_event_attr 
*miss_attr,
         * used in L1 cache, second to capture accurate value that does not
         * include cache misses incurred because of instruction loads.
         */
-       rdpmcl(hit_pmcnum, hits_before);
-       rdpmcl(miss_pmcnum, miss_before);
+       rdpmc(hit_pmcnum, hits_before);
+       rdpmc(miss_pmcnum, miss_before);
        /*
         * From SDM: Performing back-to-back fast reads are not guaranteed
         * to be monotonic.
@@ -1028,8 +1028,8 @@ static int measure_residency_fn(struct perf_event_attr 
*miss_attr,
         * before proceeding.
         */
        rmb();
-       rdpmcl(hit_pmcnum, hits_before);
-       rdpmcl(miss_pmcnum, miss_before);
+       rdpmc(hit_pmcnum, hits_before);
+       rdpmc(miss_pmcnum, miss_before);
        /*
         * Use LFENCE to ensure all previous instructions are retired
         * before proceeding.
@@ -1051,8 +1051,8 @@ static int measure_residency_fn(struct perf_event_attr 
*miss_attr,
         * before proceeding.
         */
        rmb();
-       rdpmcl(hit_pmcnum, hits_after);
-       rdpmcl(miss_pmcnum, miss_after);
+       rdpmc(hit_pmcnum, hits_after);
+       rdpmc(miss_pmcnum, miss_after);
        /*
         * Use LFENCE to ensure all previous instructions are retired
         * before proceeding.
-- 
2.49.0