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Re: [PATCH v3 2/7] arm/mpu: Provide access to the MPU region from the C code
- To: Julien Grall <julien@xxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Tue, 15 Apr 2025 08:08:55 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Tue, 15 Apr 2025 08:09:41 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH v3 2/7] arm/mpu: Provide access to the MPU region from the C code
Hi Julien,
>>>> +/*
>>>> + * The following are needed for the case generators
>>>> GENERATE_WRITE_PR_REG_CASE
>>>> + * and GENERATE_READ_PR_REG_CASE with num==0
>>>> + */
>>>> +#define PRBAR0_EL2 PRBAR_EL2
>>>> +#define PRLAR0_EL2 PRLAR_EL2
>>>
>>> Rather than aliasing, shouldn't we just rename PR{B,L}AR_EL2 to
>>> PR{B,L}AR0_EL2? This would the code mixing between the two.
>> PR{B,L}AR0_ELx does not exists really, the PR{B,L}AR<n>_ELx exists for
>> n=1..15, here I’m only using this “alias” for the generator,
>> but PR{B,L}AR_EL2 are the real register.
>
> In this case, can PR{B,L}AR0_EL2 defined in mm.c so they are not used
> anywhere else?
So this was the case in my previous serie, but Ayan asked me to put them in
here because PRBAR_EL2 is arm64 specific, not sure now, shall we move it back
and protect it with CONFIG_ARM_64?
>>>>
>>>> }
>>>> +/* Utility function to be used whenever MPU regions are modified */
>>>> +static inline void context_sync_mpu(void)
>>>> +{
>>>> + /*
>>>> + * ARM DDI 0600B.a, C1.7.1
>>>> + * Writes to MPU registers are only guaranteed to be visible
>>>> following a
>>>> + * Context synchronization event and DSB operation.
>>>
>>> I know we discussed about this before. I find odd that the specification
>>> says "context synchronization event and DSB operation". At least to me, it
>>> implies "isb + dsb" not the other way around. Has this been clarified in
>>> newer version of the specification?
>> unfortunately no, I’m looking into the latest one (Arm® Architecture
>> Reference Manual Supplement Armv8, for R-profile AArch64 architecture
>> 0600B.a) but it has the same wording, however
>> I spoke internally with Cortex-R architects and they told me to use DSB+ISB
>
> So you didn't speak with the ArmV8-R architects? Asking because we are
> writing code for ArmV8-R (so not only Cortex-R).
>
> In any case, I still think this is something that needs to be clarified
> in the specification. So people that don't have access to the Arm internal
> architects know the correct sequence. Is this something you can follow-up on?
Yes I will follow up this one
Cheers,
Luca
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