[RFC PATCH] x86/amd: Add support for AMD TCE

["Teddy Astie" <teddy.astie@xxxxxxxxxx>]

AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR 
to optimize
some TLB flushes. Enable this flag if supported by hardware.

AMD Architecture Developer Manual describe this feature as follow
> Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID 
> instructions operate
> on TLB entries. When this bit is 0, these instructions remove the target PTE 
> from the
> TLB as well as all upper-level table entries that are cached in the TLB, 
> whether or not
> they are associated with the target PTE. When this bit is set, these 
> instructions will
> remove the target PTE and only those upper-level entries that lead to the 
> target PTE in
> the page table hierarchy, leaving unrelated upper-level entries intact. This 
> may provide
> a performance benefit.

Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
---
RFC:
 - is this change actually safe ?
 - should we add a tce/no-tce option to opt-in/out this feature ?
 - is this flag enabled at the right moment during boot ?
---
 xen/arch/x86/include/asm/cpufeature.h       | 1 +
 xen/arch/x86/include/asm/msr-index.h        | 1 +
 xen/arch/x86/setup.c                        | 7 +++++++
 xen/arch/x86/smpboot.c                      | 3 +++
 xen/include/public/arch-x86/cpufeatureset.h | 1 +
 5 files changed, 13 insertions(+)

diff --git a/xen/arch/x86/include/asm/cpufeature.h 
b/xen/arch/x86/include/asm/cpufeature.h
index 05399fb9c9..ab6d07b767 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -114,6 +114,7 @@ static inline bool boot_cpu_has(unsigned int feat)
 #define cpu_has_xop             boot_cpu_has(X86_FEATURE_XOP)
 #define cpu_has_skinit          boot_cpu_has(X86_FEATURE_SKINIT)
 #define cpu_has_fma4            boot_cpu_has(X86_FEATURE_FMA4)
+#define cpu_has_tce             boot_cpu_has(X86_FEATURE_TCE)
 #define cpu_has_tbm             boot_cpu_has(X86_FEATURE_TBM)
 
 /* CPUID level 0x0000000D:1.eax */
diff --git a/xen/arch/x86/include/asm/msr-index.h 
b/xen/arch/x86/include/asm/msr-index.h
index 22d9e76e55..d7b3a4bc40 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -200,6 +200,7 @@
 #define  EFER_NXE                           (_AC(1, ULL) << 11) /* No Execute 
Enable */
 #define  EFER_SVME                          (_AC(1, ULL) << 12) /* Secure 
Virtual Machine Enable */
 #define  EFER_FFXSE                         (_AC(1, ULL) << 14) /* Fast 
FXSAVE/FXRSTOR */
+#define  EFER_TCE                           (_AC(1, ULL) << 15) /* Translation 
Cache Extensions */
 #define  EFER_AIBRSE                        (_AC(1, ULL) << 21) /* Automatic 
IBRS Enable */
 
 #define EFER_KNOWN_MASK \
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index d70abb7e0c..96f200f853 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -2008,6 +2008,13 @@ void asmlinkage __init noreturn __start_xen(void)
     if ( cpu_has_pku )
         set_in_cr4(X86_CR4_PKE);
 
+    if ( boot_cpu_has(X86_FEATURE_TCE) )
+    {
+        printk("Enabling AMD TCE\n");
+
+        write_efer(read_efer() | EFER_TCE);
+    }
+
     if ( opt_invpcid && cpu_has_invpcid )
         use_invpcid = true;
 
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 54207e6d88..fbd1710720 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -372,6 +372,9 @@ void asmlinkage start_secondary(void *unused)
 
     microcode_update_one();
 
+    if ( boot_cpu_has(X86_FEATURE_TCE) )
+        write_efer(read_efer() | EFER_TCE);
+
     /*
      * If any speculative control MSRs are available, apply Xen's default
      * settings.  Note: These MSRs may only become available after loading
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index cc6e984a88..a0c8d561fb 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT,        3*32+12) /*   SKINIT/STGI 
instructions */
 XEN_CPUFEATURE(WDT,           3*32+13) /*   Watchdog timer */
 XEN_CPUFEATURE(LWP,           3*32+15) /*   Light Weight Profiling */
 XEN_CPUFEATURE(FMA4,          3*32+16) /*A  4 operands MAC instructions */
+XEN_CPUFEATURE(TCE,           3*32+17) /*   Translation Cache Extension 
support */
 XEN_CPUFEATURE(NODEID_MSR,    3*32+19) /*   NodeId MSR */
 XEN_CPUFEATURE(TBM,           3*32+21) /*A  trailing bit manipulations */
 XEN_CPUFEATURE(TOPOEXT,       3*32+22) /*   topology extensions CPUID leafs */
-- 
2.47.2



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

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