[RFC PATCH v1 08/15] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions

["Xin Li (Intel)" <xin@xxxxxxxxx>]

The immediate form of MSR access instructions are primarily motivated
by performance, not code size: by having the MSR number in an immediate,
it is available *much* earlier in the pipeline, which allows the
hardware much more leeway about how a particular MSR is handled.

Use a scattered CPU feature bit for MSR immediate form instructions.

Suggested-by: Borislav Petkov <bp@xxxxxxxxx>
Signed-off-by: Xin Li (Intel) <xin@xxxxxxxxx>
---
 arch/x86/include/asm/cpufeatures.h | 19 ++++++++++---------
 arch/x86/kernel/cpu/scattered.c    |  1 +
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 6c2c152d8a67..a742a3d34712 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -472,15 +472,16 @@
  *
  * Reuse free bits when adding new feature flags!
  */
-#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* "amd_lbr_pmc_freeze" AMD 
LBR and PMC Freeze */
-#define X86_FEATURE_CLEAR_BHB_LOOP     (21*32+ 1) /* Clear branch history at 
syscall entry using SW loop */
-#define X86_FEATURE_BHI_CTRL           (21*32+ 2) /* BHI_DIS_S HW control 
available */
-#define X86_FEATURE_CLEAR_BHB_HW       (21*32+ 3) /* BHI_DIS_S HW control 
enabled */
-#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch 
history at vmexit using SW loop */
-#define X86_FEATURE_AMD_FAST_CPPC      (21*32 + 5) /* Fast CPPC */
-#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core 
Topology */
-#define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification 
*/
-#define X86_FEATURE_PREFER_YMM         (21*32 + 8) /* Avoid ZMM registers due 
to downclocking */
+#define X86_FEATURE_AMD_LBR_PMC_FREEZE         (21*32+ 0) /* 
"amd_lbr_pmc_freeze" AMD LBR and PMC Freeze */
+#define X86_FEATURE_CLEAR_BHB_LOOP             (21*32+ 1) /* Clear branch 
history at syscall entry using SW loop */
+#define X86_FEATURE_BHI_CTRL                   (21*32+ 2) /* BHI_DIS_S HW 
control available */
+#define X86_FEATURE_CLEAR_BHB_HW               (21*32+ 3) /* BHI_DIS_S HW 
control enabled */
+#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT   (21*32+ 4) /* Clear branch 
history at vmexit using SW loop */
+#define X86_FEATURE_AMD_FAST_CPPC              (21*32+ 5) /* Fast CPPC */
+#define X86_FEATURE_AMD_HETEROGENEOUS_CORES    (21*32+ 6) /* Heterogeneous 
Core Topology */
+#define X86_FEATURE_AMD_WORKLOAD_CLASS         (21*32+ 7) /* Workload 
Classification */
+#define X86_FEATURE_PREFER_YMM                 (21*32+ 8) /* Avoid ZMM 
registers due to downclocking */
+#define X86_FEATURE_MSR_IMM                    (21*32+ 9) /* MSR immediate 
form instructions */
 
 /*
  * BUG word(s)
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 16f3ca30626a..9eda656e9793 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = {
        { X86_FEATURE_APERFMPERF,               CPUID_ECX,  0, 0x00000006, 0 },
        { X86_FEATURE_EPB,                      CPUID_ECX,  3, 0x00000006, 0 },
        { X86_FEATURE_INTEL_PPIN,               CPUID_EBX,  0, 0x00000007, 1 },
+       { X86_FEATURE_MSR_IMM,                  CPUID_ECX,  5, 0x00000007, 1 },
        { X86_FEATURE_RRSBA_CTRL,               CPUID_EDX,  2, 0x00000007, 2 },
        { X86_FEATURE_BHI_CTRL,                 CPUID_EDX,  4, 0x00000007, 2 },
        { X86_FEATURE_CQM_LLC,                  CPUID_EDX,  1, 0x0000000f, 0 },
-- 
2.49.0