[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: Using Restricted DMA for virtio-pci
On Fri, Mar 28, 2025 at 05:40:41PM +0000, David Woodhouse wrote: > On Fri, 2025-03-21 at 18:42 +0000, David Woodhouse wrote: > > On Fri, 2025-03-21 at 14:32 -0400, Michael S. Tsirkin wrote: > > > On Fri, Mar 21, 2025 at 03:38:10PM +0000, David Woodhouse wrote: > > > > On Tue, 2021-02-09 at 14:21 +0800, Claire Chang wrote: > > > > > This series implements mitigations for lack of DMA access control on > > > > > systems without an IOMMU, which could result in the DMA accessing the > > > > > system memory at unexpected times and/or unexpected addresses, > > > > > possibly > > > > > leading to data leakage or corruption. > > > > > > > > Replying to an ancient (2021) thread which has already been merged... > > > > > > > > I'd like to be able to use this facility for virtio devices. > > > > > > > > Virtio already has a complicated relationship with the DMA API, because > > > > there were a bunch of early VMM bugs where the virtio devices where > > > > magically exempted from IOMMU protection, but the VMM lied to the guest > > > > and claimed they weren't. > > > > > > > > With the advent of confidential computing, and the VMM (or whatever's > > > > emulating the virtio device) not being *allowed* to arbitrarily access > > > > all of the guest's memory, the DMA API becomes necessary again. > > > > > > > > Either a virtual IOMMU needs to determine which guest memory the VMM > > > > may access, or the DMA API is wrappers around operations which > > > > share/unshare (or unencrypt/encrypt) the memory in question. > > > > > > > > All of which is complicated and slow, if we're looking at a minimal > > > > privileged hypervisor stub like pKVM which enforces the lack of guest > > > > memory access from VMM. > > > > > > > > I'm thinking of defining a new type of virtio-pci device which cannot > > > > do DMA to arbitrary system memory. Instead it has an additional memory > > > > BAR which is used as a SWIOTLB for bounce buffering. > > > > > > > > The driver for it would look much like the existing virtio-pci device > > > > except that it would register the restricted-dma region first (and thus > > > > the swiotlb dma_ops), and then just go through the rest of the setup > > > > like any other virtio device. > > > > > > > > That seems like it ought to be fairly simple, and seems like a > > > > reasonable way to allow an untrusted VMM to provide virtio devices with > > > > restricted DMA access. > > > > > > > > While I start actually doing the typing... does anyone want to start > > > > yelling at me now? Christoph? mst? :) > > > > > > > > > I don't mind as such (though I don't understand completely), but since > > > this is changing the device anyway, I am a bit confused why you can't > > > just set the VIRTIO_F_ACCESS_PLATFORM feature bit? This forces DMA API > > > which will DTRT for you, will it not? > > > > That would be necessary but not sufficient. ... could you explain pls? > My first cut at a proposed spec change looks something like this. I'll > post it to the virtio-comment list once I've done some corporate > bureaucracy and when the list stops sending me python tracebacks in > response to my subscribe request. the linux foundation one does this? maybe poke at the admins. > In the meantime I'll hack up some QEMU and guest Linux driver support > to match. > > diff --git a/content.tex b/content.tex > index c17ffa6..1e6e1d6 100644 > --- a/content.tex > +++ b/content.tex > @@ -773,6 +773,9 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved > Feature Bits} > Currently these device-independent feature bits are defined: > > \begin{description} > + \item[VIRTIO_F_SWIOTLB (27)] This feature indicates that the device > + provides a memory region which is to be used for bounce buffering, > + rather than permitting direct memory access to system memory. > \item[VIRTIO_F_INDIRECT_DESC (28)] Negotiating this feature indicates > that the driver can use descriptors with the VIRTQ_DESC_F_INDIRECT > flag set, as described in \ref{sec:Basic Facilities of a Virtio > @@ -885,6 +888,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved > Feature Bits} > VIRTIO_F_ACCESS_PLATFORM is not offered, then a driver MUST pass only > physical > addresses to the device. > > +A driver SHOULD accept VIRTIO_F_SWIOTLB if it is offered, and it MUST > +then pass only addresses within the Software IOTLB bounce buffer to the > +device. > + > A driver SHOULD accept VIRTIO_F_RING_PACKED if it is offered. > > A driver SHOULD accept VIRTIO_F_ORDER_PLATFORM if it is offered. > @@ -921,6 +928,10 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved > Feature Bits} > A device MAY fail to operate further if VIRTIO_F_ACCESS_PLATFORM is not > accepted. > > +A device MUST NOT offer VIRTIO_F_SWIOTLB if its transport does not > +provide a Software IOTLB bounce buffer. > +A device MAY fail to operate further if VIRTIO_F_SWIOTLB is not accepted. > + > If VIRTIO_F_IN_ORDER has been negotiated, a device MUST use > buffers in the same order in which they have been available. > > diff --git a/transport-pci.tex b/transport-pci.tex > index a5c6719..23e0d57 100644 > --- a/transport-pci.tex > +++ b/transport-pci.tex > @@ -129,6 +129,7 @@ \subsection{Virtio Structure PCI > Capabilities}\label{sec:Virtio Transport Option > \item ISR Status > \item Device-specific configuration (optional) > \item PCI configuration access > +\item SWIOTLB bounce buffer > \end{itemize} > > Each structure can be mapped by a Base Address register (BAR) belonging to > @@ -188,6 +189,8 @@ \subsection{Virtio Structure PCI > Capabilities}\label{sec:Virtio Transport Option > #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 > /* Vendor-specific data */ > #define VIRTIO_PCI_CAP_VENDOR_CFG 9 > +/* Software IOTLB bounce buffer */ > +#define VIRTIO_PCI_CAP_SWIOTLB 10 > \end{lstlisting} > > Any other value is reserved for future use. > @@ -744,6 +747,36 @@ \subsubsection{Vendor data capability}\label{sec:Virtio > The driver MUST qualify the \field{vendor_id} before > interpreting or writing into the Vendor data capability. > > +\subsubsection{Software IOTLB bounce buffer capability}\label{sec:Virtio > +Transport Options / Virtio Over PCI Bus / PCI Device Layout / > +Software IOTLB bounce buffer capability} > + > +The optional Software IOTLB bounce buffer capability allows the > +device to provide a memory region which can be used by the driver > +driver for bounce buffering. This allows a device on the PCI > +transport to operate without DMA access to system memory addresses. > + > +The Software IOTLB region is referenced by the > +VIRTIO_PCI_CAP_SWIOTLB capability. Bus addresses within the referenced > +range are not subject to the requirements of the VIRTIO_F_ORDER_PLATFORM > +capability, if negotiated. why not? an optimization? A mix of swiotlb and system memory might be very challenging from POV of ordering. > + > +\devicenormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio > +Transport Options / Virtio Over PCI Bus / PCI Device Layout / > +Software IOTLB bounce buffer capability} > + > +Devices which present the Software IOTLB bounce buffer capability > +SHOULD also offer the VIRTIO_F_SWIOTLB feature. > + > +\drivernormative{\paragraph}{Software IOTLB bounce buffer capability}{Virtio > +Transport Options / Virtio Over PCI Bus / PCI Device Layout / > +Software IOTLB bounce buffer capability} > + > +The driver SHOULD use the offered buffer in preference to passing system > +memory addresses to the device. Even if not using VIRTIO_F_SWIOTLB? Is that really necessary? > If the driver accepts the VIRTIO_F_SWIOTLB > +feature, then the driver MUST use the offered buffer and never pass system > +memory addresses to the device. > + > \subsubsection{PCI configuration access capability}\label{sec:Virtio > Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI > configuration access capability} > > The VIRTIO_PCI_CAP_PCI_CFG capability >
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