[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v3 3/3] PCI/MSI: Convert pci_msi_ignore_mask to per MSI domain flag
On Tue, Mar 25, 2025 at 10:20:43AM +0100, Thomas Gleixner wrote: > On Tue, Mar 25 2025 at 09:11, Thomas Gleixner wrote: > > > On Mon, Mar 24 2025 at 20:18, Roger Pau Monné wrote: > >> On Mon, Mar 24, 2025 at 07:58:14PM +0100, Daniel Gomez wrote: > >>> The issue is that info appears to be uninitialized. So, this worked for > >>> me: > >> > >> Indeed, irq_domain->host_data is NULL, there's no msi_domain_info. As > >> this is x86, I was expecting x86 ot always use > >> x86_init_dev_msi_info(), but that doesn't seem to be the case. I > >> would like to better understand this. > > > > Indeed. On x86 this should not happen at all. On architectures, which do > > not use (hierarchical) interrupt domains, it will return NULL. > > > > So I really want to understand why this happens on x86 before such a > > "fix" is deployed. > > So after staring at it some more it's clear. Without XEN, the domain > returned is the MSI parent domain, which is the vector domain in that > setup. That does not have a domain info set. But on legacy architectures > there is not even a domain. > > It's really wonderful that we have a gazillion ways to manage the > backends of PCI/MSI.... > > So none of the suggested pointer checks will cover it correctly. Though > there is already a function which allows to query MSI domain flags > independent of the underlying insanity. Sorry for not catching it in > review. > > Untested patch below. > > Thanks, > > tglx > --- > drivers/pci/msi/msi.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > > --- a/drivers/pci/msi/msi.c > +++ b/drivers/pci/msi/msi.c > @@ -285,8 +285,6 @@ static void pci_msi_set_enable(struct pc > static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, > struct irq_affinity_desc *masks) > { > - const struct irq_domain *d = dev_get_msi_domain(&dev->dev); > - const struct msi_domain_info *info = d->host_data; > struct msi_desc desc; > u16 control; > > @@ -297,7 +295,7 @@ static int msi_setup_msi_desc(struct pci > /* Lies, damned lies, and MSIs */ > if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING) > control |= PCI_MSI_FLAGS_MASKBIT; > - if (info->flags & MSI_FLAG_NO_MASK) > + if (pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY)) > control &= ~PCI_MSI_FLAGS_MASKBIT; > > desc.nvec_used = nvec; > @@ -605,20 +603,18 @@ static void __iomem *msix_map_region(str > */ > void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc) > { > - const struct irq_domain *d = dev_get_msi_domain(&dev->dev); > - const struct msi_domain_info *info = d->host_data; > - > desc->nvec_used = 1; > desc->pci.msi_attrib.is_msix = 1; > desc->pci.msi_attrib.is_64 = 1; > desc->pci.msi_attrib.default_irq = dev->irq; > desc->pci.mask_base = dev->msix_base; > - desc->pci.msi_attrib.can_mask = !(info->flags & > MSI_FLAG_NO_MASK) && > - > !desc->pci.msi_attrib.is_virtual; > > - if (desc->pci.msi_attrib.can_mask) { > + > + if (!pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY) && > + !desc->pci.msi_attrib.is_virtual) { > void __iomem *addr = pci_msix_desc_addr(desc); > > + desc->pci.msi_attrib.can_mask = true; can_mask is u8. > desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); > } > } > @@ -715,8 +711,6 @@ static int msix_setup_interrupts(struct > static int msix_capability_init(struct pci_dev *dev, struct msix_entry > *entries, > int nvec, struct irq_affinity *affd) > { > - const struct irq_domain *d = dev_get_msi_domain(&dev->dev); > - const struct msi_domain_info *info = d->host_data; > int ret, tsize; > u16 control; > > @@ -747,7 +741,7 @@ static int msix_capability_init(struct p > /* Disable INTX */ > pci_intx_for_msi(dev, 0); > > - if (!(info->flags & MSI_FLAG_NO_MASK)) { > + if (!pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY)) { > /* > * Ensure that all table entries are masked to prevent > * stale entries from firing in a crash kernel. It works, thanks! For the final patch: Tested-by: Daniel Gomez <da.gomez@xxxxxxxxxxx> Daniel
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