[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v2 1/4] xen/arm32: Initialize MM specific registers in enable_mmu
All the memory management specific registers are initialized in enable_mmu. Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx> --- Changes from - v1 - HTCR and HMAIR{0,1} are not set together with the other memory management registers in enable_mmu() Similar changes are to be done in arm64 as well. I prefer to do that in a separate patch so that all the arm32 changes are kept together in this series. xen/arch/arm/arm32/head.S | 14 -------------- xen/arch/arm/arm32/mmu/head.S | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4ff5c220bc..50da179f81 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -218,20 +218,6 @@ cpu_init: add pc, r1, r10 /* Call paddr(init func) */ cpu_init_done: - /* Set up memory attribute type tables */ - mov_w r0, MAIR0VAL - mov_w r1, MAIR1VAL - mcr CP32(r0, HMAIR0) - mcr CP32(r1, HMAIR1) - - /* - * Set up the HTCR: - * PT walks use Inner-Shareable accesses, - * PT walks are write-back, write-allocate in both cache levels, - * Full 32-bit address space goes through this table. - */ - mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) - mcr CP32(r0, HTCR) mov_w r0, HSCTLR_SET mcr CP32(r0, HSCTLR) diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S index 1e2bbf0c82..8fa74bd556 100644 --- a/xen/arch/arm/arm32/mmu/head.S +++ b/xen/arch/arm/arm32/mmu/head.S @@ -279,6 +279,21 @@ ENDPROC(create_page_tables) enable_mmu: PRINT("- Turning on paging -\r\n") + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + /* + * Set up the HTCR: + * PT walks use Inner-Shareable accesses, + * PT walks are write-back, write-allocate in both cache levels, + * Full 32-bit address space goes through this table. + */ + mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) + mcr CP32(r0, HTCR) + /* * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. -- 2.25.1
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