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Re: [PATCH] RISCV/bitops: Use Zbb to provide arch-optimised bitops
- To: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Wed, 26 Feb 2025 23:55:42 +0000
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- Delivery-date: Wed, 26 Feb 2025 23:56:07 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 26/02/2025 9:01 pm, Oleksii Kurochko wrote:
>
>
> On 2/26/25 6:20 PM, Andrew Cooper wrote:
>> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
>> ---
>> CC: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
>> Depends on "xen/riscv: make zbb as mandatory"
>> ---
>> xen/arch/riscv/include/asm/bitops.h | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/xen/arch/riscv/include/asm/bitops.h
>> b/xen/arch/riscv/include/asm/bitops.h
>> index d22eec1e87c7..df3df93520c5 100644
>> --- a/xen/arch/riscv/include/asm/bitops.h
>> +++ b/xen/arch/riscv/include/asm/bitops.h
>> @@ -125,6 +125,13 @@ static inline void clear_bit(int nr, volatile void *p)
>> #undef NOT
>> #undef __AMO
>>
>> +#define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0)
>> +#define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0)
>> +#define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0)
>> +#define arch_flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0)
>> +
>> +#define arch_heightl(x) __builtin_popcountl(x)
>> +
>> #endif /* ASM__RISCV__BITOPS_H */
>>
>> /*
> LGRM: Reviewed-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
Thanks. This form is much easier than making alternatives for it.
> Thanks.
>> base-commit: 7cf163879c5add0a4f7f9c987b61f04f8f7051b1
>> prerequisite-patch-id: 9ee1f7ebf5d34b1c565ee2d3d4fb319164bb8bcd
>> prerequisite-patch-id: 8a05c87c8d051a3ac0820887f676bbd318e4ae88
>> prerequisite-patch-id: 6b56e42d130d8b5ee39457b6760b05cc6e16b049
>> prerequisite-patch-id: c139f1f5741d695cd5e5aa6be904edcb61b73885
>> prerequisite-patch-id: 99f8b701000e9ee11060934e627a988ddf9aaaa7
> Could you please tell me how do you generate this one?
In gitconfig,
[format]
useAutoBase = "whenAble"
or --base=auto on a git format-patch command.
This is a poor example. Those prereq ids are:
* 307e136282d8 - (HEAD -> riscv-isa) RISCV/bitops: Use Zbb to provide
arch-optimised bitops (7 hours ago) <Andrew Cooper>
* 519dcd50e4cd - xen/riscv: make zbb as mandatory (12 hours ago)
<Oleksii Kurochko>
* c9bf2a9ac22c - xen/riscv: identify specific ISA supported by cpu (12
hours ago) <Oleksii Kurochko>
* 9014de63aa14 - automation: drop debian:11-riscv64 container (12 hours
ago) <Oleksii Kurochko>
* 5febb98d11f3 - xen/riscv: drop CONFIG_RISCV_ISA_RV64G (12 hours ago)
<Oleksii Kurochko>
* 5a7c9fd746af - xen/README: add compiler and binutils versions for
RISCV-64 (12 hours ago) <Oleksii Kurochko>
* 7cf163879c5a - (xenbits/staging, xenbits/master, upstream/staging,
upstream/master, origin/staging, origin/master, origin/HEAD, staging,
pending, master) PPC: Activate UBSAN in testing (12 hours ago) <Andrew
Cooper>
as I pulled your series in locally.
~Andrew
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