[PATCH for 4.21 v6 1/2] xen/riscv: drop CONFIG_RISCV_ISA_RV64G

[Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>]

'G' stands for "imafd_zicsr_zifencei".

Extensions 'f' and 'd' aren't really needed for Xen, and allowing floating
point registers to be used can lead to crashes.

Extensions 'i', 'm', 'a', 'zicsr', and 'zifencei' are necessary for the
operation of Xen, which is why they are used explicitly (unconditionally)
in -march.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
---
Changes in v6:
 - new patch for the patch series.
---
 xen/arch/riscv/Kconfig | 10 ----------
 xen/arch/riscv/arch.mk |  9 +++++++--
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig
index 00f329054c..5b72937139 100644
--- a/xen/arch/riscv/Kconfig
+++ b/xen/arch/riscv/Kconfig
@@ -28,16 +28,6 @@ choice
        help
          This selects the base ISA extensions that Xen will target.
 
-config RISCV_ISA_RV64G
-       bool "RV64G"
-       help
-         Use the RV64I base ISA, plus
-         "M" for multiply/divide,
-         "A" for atomic instructions,
-         “F”/"D" for  {single/double}-precision floating-point instructions,
-         "Zicsr" for control and status register access,
-         "Zifencei" for instruction-fetch fence.
-
 endchoice
 
 config RISCV_ISA_C
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 17827c302c..1819ec17eb 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -6,8 +6,13 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS))
 riscv-abi-$(CONFIG_RISCV_32) := -mabi=ilp32
 riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64
 
-riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g
-riscv-march-$(CONFIG_RISCV_ISA_C)       := $(riscv-march-y)c
+riscv-march-$(CONFIG_RISCV_64) := rv64
+
+riscv-march-y := $(riscv-march-y)ima
+
+riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
+
+riscv-march-y := $(riscv-march-y)_zicsr_zifencei
 
 riscv-generic-flags := $(riscv-abi-y) -march=$(riscv-march-y)
 
-- 
2.48.1