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Re: Config space access to Mediatek MT7922 doesn't work after device reset in Xen PV dom0 (regression, Linux 6.12)

From: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>

Date: Thu, 30 Jan 2025 05:55:55 +0100

Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>, Jürgen Groß <jgross@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>, xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, regressions@xxxxxxxxxxxxxxx, Felix Fietkau <nbd@xxxxxxxx>, Lorenzo Bianconi <lorenzo@xxxxxxxxxx>, Ryder Lee <ryder.lee@xxxxxxxxxxxx>

Delivery-date: Thu, 30 Jan 2025 04:56:26 +0000

Feedback-id: i1568416f:Fastmail

List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Wed, Jan 29, 2025 at 12:48:25PM -0600, Bjorn Helgaas wrote: > On Wed, Jan 29, 2025 at 03:10:49AM +0100, Marek Marczykowski-Górecki wrote: > > On Tue, Jan 28, 2025 at 07:15:26PM -0600, Bjorn Helgaas wrote: > > > On Fri, Jan 17, 2025 at 01:05:30PM +0100, Marek Marczykowski-Górecki > > > wrote: > > > > After updating PV dom0 to Linux 6.12, The Mediatek MT7922 device reports > > > > all 0xff when accessing its config space. This happens only after device > > > > reset (which is also triggered when binding the device to the > > > > xen-pciback driver). > > > > > > Thanks for the report and for all the debugging you've already done! > > > > > > > Reproducer: > > > > > > > > # lspci -xs 01:00.0 > > > > 01:00.0 Network controller: MEDIATEK Corp. MT7922 802.11ax PCI > > > > Express Wireless Network Adapter > > > > 00: c3 14 16 06 00 00 10 00 00 00 80 02 10 00 00 00 > > > > ... > > > > # echo 1 > /sys/bus/pci/devices/0000:01:00.0/reset > > > > # lspci -xs 01:00.0 > > > > 01:00.0 Network controller: MEDIATEK Corp. MT7922 802.11ax PCI > > > > Express Wireless Network Adapter > > > > 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > > > > > > > > The same operation done on Linux 6.12 running without Xen works fine. > > > > > > > > git bisect points at: > > > > > > > > commit d591f6804e7e1310881c9224d72247a2b65039af > > > > Author: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > > > > Date: Tue Aug 27 18:48:46 2024 -0500 > > > > > > > > PCI: Wait for device readiness with Configuration RRS > > > > > > > > part of that commit: > > > > @@ -1311,9 +1320,15 @@ static int pci_dev_wait(struct pci_dev *dev, > > > > char *reset_type, int timeout) > > > > return -ENOTTY; > > > > } > > > > > > > > - pci_read_config_dword(dev, PCI_COMMAND, &id); > > > > - if (!PCI_POSSIBLE_ERROR(id)) > > > > - break; > > > > + if (root && root->config_crs_sv) { > > > > + pci_read_config_dword(dev, PCI_VENDOR_ID, &id); > > > > + if (!pci_bus_crs_vendor_id(id)) > > > > + break; > > > > + } else { > > > > + pci_read_config_dword(dev, PCI_COMMAND, &id); > > > > + if (!PCI_POSSIBLE_ERROR(id)) > > > > + break; > > > > + } > > > > > > > > > > > > Adding some debugging, the PCI_VENDOR_ID read in pci_dev_wait() returns > > > > initially 0xffffffff. If I extend the condition with > > > > "&& !PCI_POSSIBLE_ERROR(id)", then the issue disappear. But reading the > > > > patch description, it would break VF. > > > > I'm not sure where the issue is, but given it breaks only when running > > > > with Xen, I guess something is wrong with "Configuration RRS Software > > > > Visibility" in that case. > > > > > > I'm missing something. If you get 0xffffffff, that is not the 0x0001 > > > Vendor ID, so pci_dev_wait() should exit immediately. > > > > I'm not sure what is going on there either, but my _guess_ is that the > > loop exits too early due to the above. And it makes some further actions > > to fail. > > Seems like a good guess worth investigating. Maybe log all config > accesses to this device after the FLR and see what we're doing? I've added logging of all config read/write to this device. Full log at [1]. A little explanation: - it's done in pci_conf_read/pci_conf_write in https://xenbits.xen.org/gitweb/?p=xen.git;a=blob;f=xen/arch/x86/pci.c;h=97b792e578f1093194466081ad3651ade21cae7d;hb=HEAD - cf8 means cf8 port value (BDF + register) - bytes is read/write size (1/2/4) - offset is the offset in the register (on top of cf8), but not in data - data is either retrieved value, or written value, depending on function - it's logging only accesses to 01:00.0 interesting part: lspci before reset: (XEN) d0v3 conf read cf8 0x80010000 bytes 4 offset 0 data 0x61614c3 (XEN) d0v3 conf read cf8 0x80010004 bytes 4 offset 0 data 0x100000 (XEN) d0v3 conf read cf8 0x80010008 bytes 4 offset 0 data 0x2800000 (XEN) d0v3 conf read cf8 0x8001000c bytes 4 offset 0 data 0x10 (XEN) d0v3 conf read cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v3 conf read cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v3 conf read cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v3 conf read cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x80010028 bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x8001002c bytes 4 offset 0 data 0xe61614c3 (XEN) d0v3 conf read cf8 0x80010030 bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x80010034 bytes 4 offset 0 data 0x80 (XEN) d0v3 conf read cf8 0x80010038 bytes 4 offset 0 data 0 (XEN) d0v3 conf read cf8 0x8001003c bytes 4 offset 0 data 0x1ff (XEN) d0v3 conf read cf8 0x80010080 bytes 4 offset 0 data 0x2e010 (XEN) d0v3 conf read cf8 0x800100e0 bytes 4 offset 0 data 0x18af805 (XEN) d0v3 conf read cf8 0x800100f8 bytes 4 offset 0 data 0xc8030001 reset: (XEN) d0v1 conf read cf8 0x800100fc bytes 2 offset 0 data 0x8 (XEN) d0v1 conf read cf8 0x800100fc bytes 2 offset 0 data 0x8 (XEN) d0v1 conf read cf8 0x8001008c bytes 4 offset 0 data 0x145dc12 (XEN) d0v1 conf read cf8 0x80010000 bytes 4 offset 0 data 0x61614c3 (XEN) d0v1 conf read cf8 0x80010004 bytes 4 offset 0 data 0x100000 (XEN) d0v1 conf read cf8 0x80010008 bytes 4 offset 0 data 0x2800000 (XEN) d0v1 conf read cf8 0x8001000c bytes 4 offset 0 data 0x10 (XEN) d0v1 conf read cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v1 conf read cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v1 conf read cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v1 conf read cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x80010028 bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x8001002c bytes 4 offset 0 data 0xe61614c3 (XEN) d0v1 conf read cf8 0x80010030 bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x80010034 bytes 4 offset 0 data 0x80 (XEN) d0v1 conf read cf8 0x80010038 bytes 4 offset 0 data 0 (XEN) d0v1 conf read cf8 0x8001003c bytes 4 offset 0 data 0x1ff (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 0 data 0x2910 (XEN) d0v1 conf read cf8 0x80010090 bytes 2 offset 0 data 0x1c2 (XEN) d0v1 conf read cf8 0x800100a8 bytes 2 offset 0 data 0x400 (XEN) d0v1 conf read cf8 0x800100b0 bytes 2 offset 0 data 0x2 (XEN) d0v1 conf read cf8 0x80010004 bytes 2 offset 2 data 0x10 (XEN) d0v1 conf read cf8 0x80010034 bytes 1 offset 0 data 0x80 (XEN) d0v1 conf read cf8 0x80010080 bytes 2 offset 0 data 0xe010 (XEN) d0v1 conf read cf8 0x800100e0 bytes 2 offset 0 data 0xf805 (XEN) d0v1 conf read cf8 0x800100f8 bytes 2 offset 0 data 0x1 (XEN) d0v1 conf write cf8 0x80010004 bytes 2 offset 0 data 0x400 (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 2 data 0x9 (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 0 data 0x2910 (XEN) d0v1 conf write cf8 0x80010088 bytes 2 offset 0 data 0xa910 (XEN) d0v2 conf read cf8 0x80010000 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf read cf8 0x80010090 bytes 2 offset 0 data 0xffff (XEN) d0v2 conf write cf8 0x80010090 bytes 2 offset 0 data 0xfffc (XEN) d0v2 conf write cf8 0x80010090 bytes 2 offset 0 data 0xffff (XEN) d0v2 conf write cf8 0x80010088 bytes 2 offset 0 data 0x2910 (XEN) d0v2 conf write cf8 0x80010090 bytes 2 offset 0 data 0x1c2 (XEN) d0v2 conf write cf8 0x800100a8 bytes 2 offset 0 data 0x400 (XEN) d0v2 conf write cf8 0x800100b0 bytes 2 offset 0 data 0x2 (XEN) d0v2 conf read cf8 0x8001003c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001003c bytes 4 offset 0 data 0x1ff (XEN) d0v2 conf read cf8 0x80010038 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010038 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010034 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010034 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010030 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010030 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001002c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001002c bytes 4 offset 0 data 0xe61614c3 (XEN) d0v2 conf read cf8 0x80010028 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010028 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010024 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010024 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010020 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010020 bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x8001001c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001001c bytes 4 offset 0 data 0 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010018 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010018 bytes 4 offset 0 data 0x90b00004 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010014 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010014 bytes 4 offset 0 data 0x80 (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x80010010 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010010 bytes 4 offset 0 data 0x1090000c (XEN) d0v2 conf read cf8 0x8001000c bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x8001000c bytes 4 offset 0 data 0x10 (XEN) d0v2 conf read cf8 0x80010008 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010008 bytes 4 offset 0 data 0x2800000 (XEN) d0v2 conf read cf8 0x80010004 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010004 bytes 4 offset 0 data 0x100000 (XEN) d0v2 conf read cf8 0x80010000 bytes 4 offset 0 data 0xffffffff (XEN) d0v2 conf write cf8 0x80010000 bytes 4 offset 0 data 0x61614c3 (XEN) d0v2 conf read cf8 0x80010004 bytes 2 offset 2 data 0xffff (XEN) d0v2 conf read cf8 0x80010034 bytes 1 offset 0 data 0xff (XEN) d0v2 conf read cf8 0x800100fc bytes 2 offset 0 data 0xffff [1] https://gist.github.com/marmarek/b4391c71801145e52590e877c559c5e0 -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab

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