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Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature


  • To: Jan Beulich <jbeulich@xxxxxxxx>, Petr Beneš <w1benny@xxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 8 Jan 2025 12:23:28 +0000
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  • Cc: Tamas K Lengyel <tamas@xxxxxxxxxxxxx>, Alexandru Isaila <aisaila@xxxxxxxxxxxxxxx>, Petre Pircalabu <ppircalabu@xxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Wed, 08 Jan 2025 12:23:49 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 08/01/2025 7:16 am, Jan Beulich wrote:
> On 07.01.2025 18:18, Petr Beneš wrote:
>> On Tue, Jan 7, 2025 at 5:46 PM Jan Beulich <jbeulich@xxxxxxxx> wrote:
>>> Hmm ... Instead of you touching the bit in every one of the case blocks,
>>> I was expecting you to clear the bit ahead of the switch(), accepting a
>>> double update in the p2m_access_r_pw case.
>> I did consider it, but ultimately didn't like the double-update.
>> Similarly, the switch-case above does also set each bit in the
>> "case-s" individually. But I understand it's more justified there.
> Right - it's setting them to all different combinations each time.
>
>> However, if you insist, I'll fix it.
> Please do; it helps readability quite a bit in this case, imo.

I agree.

These "writes" are just bit operations on a single register.  The
compiler is pretty good at rearranging such logic.

Seeing as this is the only issue, I'm happy to fix on commit?

~Andrew



 


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