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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [RFC PATCH v2 02/10] x86: Define arch LBR feature bits
Add three featureset words corresponding to the 3 CPUID words in leaf
0x1c.
Intel SDM states that CPUID may indicate a LBR depth of up to 64.
However, since XSAVE LBR state only goes up to 32 LBRs, don't expose the
other CPUID depth bits for now.
Signed-off-by: Tu Dinh <ngoc-tu.dinh@xxxxxxxxxx>
---
xen/arch/x86/include/asm/cpufeature.h | 5 ++
xen/include/public/arch-x86/cpufeatureset.h | 28 ++++++++++-
xen/include/xen/lib/x86/cpu-policy.h | 51 ++++++++++++++++++++-
xen/lib/x86/cpuid.c | 6 +++
4 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/include/asm/cpufeature.h
b/xen/arch/x86/include/asm/cpufeature.h
index 3a06b6f297..4323ffb8cb 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -219,6 +219,11 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_rfds_no boot_cpu_has(X86_FEATURE_RFDS_NO)
#define cpu_has_rfds_clear boot_cpu_has(X86_FEATURE_RFDS_CLEAR)
+/* CPUID level 0x0000001c.eax */
+
+#define current_cpu_has_lbr_lip cpu_has(¤t_cpu_data, \
+ X86_FEATURE_LBR_LIP);
+
/* Synthesized. */
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
#define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 8fa3fb711a..86d3e61438 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -284,7 +284,7 @@ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn
*/
XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */
XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume
insns */
XEN_CPUFEATURE(PCONFIG, 9*32+18) /* PCONFIG instruction */
-XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */
+XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /*s Architectural Last Branch Record */
XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* AMX BFloat16 instruction */
XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */
@@ -379,6 +379,32 @@ XEN_CPUFEATURE(RFDS_CLEAR, 16*32+28) /*!A|
Register File(s) cleared by V
/* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */
+/* Intel-defined CPU features, CPUID level 0x0000001c.eax, word 18 */
+XEN_CPUFEATURE(LBR_DEPTH_8, 18*32+ 0) /*s Depth 8 */
+XEN_CPUFEATURE(LBR_DEPTH_16, 18*32+ 1) /*s Depth 16 */
+XEN_CPUFEATURE(LBR_DEPTH_24, 18*32+ 2) /*s Depth 24 */
+XEN_CPUFEATURE(LBR_DEPTH_32, 18*32+ 3) /*s Depth 32 */
+XEN_CPUFEATURE(LBR_DEPTH_40, 18*32+ 4) /* Depth 40 */
+XEN_CPUFEATURE(LBR_DEPTH_48, 18*32+ 5) /* Depth 48 */
+XEN_CPUFEATURE(LBR_DEPTH_56, 18*32+ 6) /* Depth 56 */
+XEN_CPUFEATURE(LBR_DEPTH_64, 18*32+ 7) /* Depth 64 */
+XEN_CPUFEATURE(LBR_DCST_RST, 18*32+30) /*s Deep C-state reset */
+XEN_CPUFEATURE(LBR_LIP, 18*32+31) /*! IP is linear IP */
+
+/* Intel-defined CPU features, CPUID level 0x0000001c.ebx, word 19 */
+XEN_CPUFEATURE(LBR_CPL_FILTER, 19*32+ 0) /*s CPL filtering */
+XEN_CPUFEATURE(LBR_BR_FILTER, 19*32+ 1) /*s Branch filtering */
+XEN_CPUFEATURE(LBR_CALL_STACK, 19*32+ 2) /*s Call stack mode */
+
+/* Intel-defined CPU features, CPUID level 0x0000001c.ecx, word 20 */
+XEN_CPUFEATURE(LBR_MISPRED, 20*32+ 0) /*s Mispredict mode */
+XEN_CPUFEATURE(LBR_TIMED, 20*32+ 1) /*s Timed mode */
+XEN_CPUFEATURE(LBR_BR_TYPE, 20*32+ 2) /*s Branch type */
+XEN_CPUFEATURE(LBR_EVENT_LOG_0, 20*32+16) /*s Event logging for counter 0
*/
+XEN_CPUFEATURE(LBR_EVENT_LOG_1, 20*32+17) /*s Event logging for counter 1
*/
+XEN_CPUFEATURE(LBR_EVENT_LOG_2, 20*32+18) /*s Event logging for counter 2
*/
+XEN_CPUFEATURE(LBR_EVENT_LOG_3, 20*32+19) /*s Event logging for counter 3
*/
+
#endif /* XEN_CPUFEATURE */
/* Clean up from a default include. Close the enum (for C). */
diff --git a/xen/include/xen/lib/x86/cpu-policy.h
b/xen/include/xen/lib/x86/cpu-policy.h
index f43e1a3b21..f3b331f36c 100644
--- a/xen/include/xen/lib/x86/cpu-policy.h
+++ b/xen/include/xen/lib/x86/cpu-policy.h
@@ -22,6 +22,9 @@
#define FEATURESET_7d1 15 /* 0x00000007:1.edx */
#define FEATURESET_m10Al 16 /* 0x0000010a.eax */
#define FEATURESET_m10Ah 17 /* 0x0000010a.edx */
+#define FEATURESET_1Ca 18 /* 0x0000001c.eax */
+#define FEATURESET_1Cb 19 /* 0x0000001c.ebx */
+#define FEATURESET_1Cc 20 /* 0x0000001c.ecx */
struct cpuid_leaf
{
@@ -85,7 +88,7 @@ unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t
ecx, uint32_t edx);
*/
const char *x86_cpuid_vendor_to_str(unsigned int vendor);
-#define CPUID_GUEST_NR_BASIC (0xdu + 1)
+#define CPUID_GUEST_NR_BASIC (0x1cu + 1)
#define CPUID_GUEST_NR_CACHE (5u + 1)
#define CPUID_GUEST_NR_FEAT (2u + 1)
#define CPUID_GUEST_NR_TOPO (1u + 1)
@@ -158,6 +161,52 @@ struct cpu_policy
uint64_t :64, :64; /* Leaf 0xb - Topology. */
uint64_t :64, :64; /* Leaf 0xc - rsvd */
uint64_t :64, :64; /* Leaf 0xd - XSTATE. */
+
+ uint64_t :64, :64; /* Leaf 0xe - rsvd */
+ uint64_t :64, :64; /* Leaf 0xf - rsvd */
+ uint64_t :64, :64; /* Leaf 0x10 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x11 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x12 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x13 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x14 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x15 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x16 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x17 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x18 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x19 - rsvd */
+ uint64_t :64, :64; /* Leaf 0x1a - rsvd */
+ uint64_t :64, :64; /* Leaf 0x1b - rsvd */
+
+ union {
+ uint32_t _1Ca;
+ struct {
+ uint32_t supported_depths:8;
+ uint32_t :22;
+ uint32_t deep_cstate_reset:1;
+ uint32_t ip_contains_lip:1;
+ } lbr_1Ca;
+ };
+ union {
+ uint32_t _1Cb;
+ struct {
+ uint32_t cpl_filter:1;
+ uint32_t br_filter:1;
+ uint32_t call_stack:1;
+ } lbr_1Cb;
+ };
+ union {
+ uint32_t _1Cc;
+ struct {
+ uint32_t mispred:1;
+ uint32_t timed:1;
+ uint32_t br_type:1;
+ uint32_t :13;
+ uint32_t event_log_0:1;
+ uint32_t event_log_1:1;
+ uint32_t event_log_2:1;
+ uint32_t event_log_3:1;
+ } lbr_1Cc;
+ };
};
} basic;
diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
index eb7698dc73..4d19349b17 100644
--- a/xen/lib/x86/cpuid.c
+++ b/xen/lib/x86/cpuid.c
@@ -81,6 +81,9 @@ void x86_cpu_policy_to_featureset(
fs[FEATURESET_7d1] = p->feat._7d1;
fs[FEATURESET_m10Al] = p->arch_caps.lo;
fs[FEATURESET_m10Ah] = p->arch_caps.hi;
+ fs[FEATURESET_1Ca] = p->basic._1Ca;
+ fs[FEATURESET_1Cb] = p->basic._1Cb;
+ fs[FEATURESET_1Cc] = p->basic._1Cc;
}
void x86_cpu_featureset_to_policy(
@@ -104,6 +107,9 @@ void x86_cpu_featureset_to_policy(
p->feat._7d1 = fs[FEATURESET_7d1];
p->arch_caps.lo = fs[FEATURESET_m10Al];
p->arch_caps.hi = fs[FEATURESET_m10Ah];
+ p->basic._1Ca = fs[FEATURESET_1Ca];
+ p->basic._1Cb = fs[FEATURESET_1Cb];
+ p->basic._1Cc = fs[FEATURESET_1Cc];
}
void x86_cpu_policy_recalc_synth(struct cpu_policy *p)
--
2.43.0
Ngoc Tu Dinh | Vates XCP-ng Developer
XCP-ng & Xen Orchestra - Vates solutions
web: https://vates.tech
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