Re: [PATCH v2 5/7] xen/riscv: implement data and instruction cache operations

[Jan Beulich <jbeulich@xxxxxxxx>]

On 11.12.2024 18:27, Oleksii Kurochko wrote:
> --- a/xen/arch/riscv/include/asm/page.h
> +++ b/xen/arch/riscv/include/asm/page.h
> @@ -7,6 +7,7 @@
>  
>  #include <xen/bug.h>
>  #include <xen/const.h>
> +#include <xen/errno.h>
>  #include <xen/types.h>
>  
>  #include <asm/atomic.h>
> @@ -148,9 +149,27 @@ static inline bool pte_is_mapping(pte_t p)
>      return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK);
>  }
>  
> +static inline int clean_and_invalidate_dcache_va_range(const void *p, 
> unsigned long size)
> +{
> +#ifdef CONFIG_QEMU
> +    return 0;
> +#else
> +    return -EOPNOTSUPP;
> +#endif
> +}
> +
> +static inline int clean_dcache_va_range(const void *p, unsigned long size)
> +{
> +#ifdef CONFIG_QEMU
> +    return 0;
> +#else
> +    return -EOPNOTSUPP;
> +#endif
> +}

So testing on real hardware will then effectively become impossible, until
someone goes and implements these?

> --- /dev/null
> +++ b/xen/arch/riscv/platforms/Kconfig
> @@ -0,0 +1,5 @@
> +config QEMU
> +     bool "QEMU aarch virt machine support"
> +     depends on RISCV_64

I understand Arm has it like this, but: Is QEMU really a sufficiently non-
ambiguous name to use? Is the RISCV_64 dependency really needed?

> +     help
> +       Enable all the required drivers for QEMU riscv64 virt emulated 
> machine.

This line looks to be slightly too long now (after you apparently unwrapped
what Arm has).

Jan