Re: [PATCH v2 1/2] xen/mpu: Map early uart when earlyprintk on

[Luca Fancellu <Luca.Fancellu@xxxxxxx>]

> On 3 Dec 2024, at 15:54, Luca Fancellu <Luca.Fancellu@xxxxxxx> wrote:
> 
> Hi Ayan,
> 
> sorry for the separate message, I've spotted another thing where I’m in doubt
> 
>> On 27 Nov 2024, at 18:39, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx> 
>> wrote:
>> 
>> CONFIG_EARLY_UART_SIZE is introduced to let user provide physical size of
>> early UART. Unlike MMU where we map a page in the virtual address space,
>> here we need to know the exact physical size to be mapped.
>> As VA == PA in case of MPU, the memory layout follows exactly the hardware
>> configuration. As a consequence, we set  EARLY_UART_VIRTUAL_ADDRESS as 
>> physical
>> address.
>> 
>> EARLY_UART_BASE_ADDRESS and EARLY_UART_SIZE should be aligned to the minimum
>> size of MPU region (ie 64 bits) as per the hardware restrictions. Refer ARM
>> DDI 0600A.d ID120821 A1.3 "A minimum protection region size of 64 bytes.".
>> 
>> UART is mapped as nGnRE region (as specified by ATTR=100 , refer G1.3.13,
>> MAIR_EL2, "---0100 Device memory nGnRE") and Doc ID - 102670_0101_02_en
>> Table 4-3, Armv8 architecture memory types (nGnRE - Corresponds to Device in
>> Armv7 architecture). Also, it is mapped as outer shareable, RW at EL2 only
>> and execution of instructions from the region is not permitted.
>> 
> 
> [...]
> 
> 
>> diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S
>> index f692fc7443..86e4019a0c 100644
>> --- a/xen/arch/arm/arm64/mpu/head.S
>> +++ b/xen/arch/arm/arm64/mpu/head.S
>> @@ -11,8 +11,10 @@
>> #define REGION_TEXT_PRBAR       0x38    /* SH=11 AP=10 XN=00 */
>> #define REGION_RO_PRBAR         0x3A    /* SH=11 AP=10 XN=10 */
>> #define REGION_DATA_PRBAR       0x32    /* SH=11 AP=00 XN=10 */
>> +#define REGION_DEVICE_PRBAR     0x22    /* SH=10 AP=00 XN=10 */
>> 
>> #define REGION_NORMAL_PRLAR     0x0f    /* NS=0 ATTR=111 EN=1 */
>> +#define REGION_DEVICE_PRLAR     0x09    /* NS=0 ATTR=100 EN=1 */
> 
> Should this point to ATTR=0 instead? From what I see on Zephyr, the pl011 is
> mapped with nGnRnE, on R82 this works fine because it will treat all device 
> memory as
> nGnRnE, but I’m not sure that this will work well on other Armv8-R aarch64 
> platforms.
> 
> I was trying to check how Linux maps pl011 but I’m kind of lost, so maybe if 
> anyone has
> more experience is more than welcome to contribute to the discussion.


Anyway, changing that to 0x01 (ATTR=0 EN=1) is giving me a weird issue in my 
branch:

"Error getting IRQ number for this serial port 0” from create_domUs(), so I’m 
not sure now
if the right value was indeed 0x09