Re: [PATCH v7 3/7] x86emul: support USER_MSR instructions

[Jan Beulich <jbeulich@xxxxxxxx>]

On 25.11.2024 16:06, Jan Beulich wrote:
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -7037,10 +7037,68 @@ x86_emulate(
>          state->simd_size = simd_none;
>          break;
>  
> -    case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 */
> -    case X86EMUL_OPC_F3(0x0f38, 0xf8): /* enqcmds r,m512 */
> +    case X86EMUL_OPC_F3(0x0f38, 0xf8): /* enqcmds r,m512 / uwrmsr r64,r32 */
> +    case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 / urdmsr r32,r64 */
> +        if ( ea.type == OP_MEM )
> +            goto enqcmd;
> +        imm1 = src.val;
> +        /* fall through */
> +    case X86EMUL_OPC_VEX_F3(7, 0xf8): /* uwrmsr r64,imm32 */
> +    case X86EMUL_OPC_VEX_F2(7, 0xf8): /* urdmsr imm32,r64 */
> +        generate_exception_if(!mode_64bit() || ea.type != OP_REG, 
> X86_EXC_UD);
> +        generate_exception_if(vex.l || vex.w, X86_EXC_UD);
> +        generate_exception_if(vex.opcx && ((modrm_reg & 7) || vex.reg != 
> 0xf),
> +                              X86_EXC_UD);
> +        vcpu_must_have(user_msr);
> +        fail_if(!ops->read_msr);
> +        if ( ops->read_msr(MSR_USER_MSR_CTL, &msr_val, ctxt) != X86EMUL_OKAY 
> )
> +        {
> +            x86_emul_reset_event(ctxt);
> +            msr_val = 0;
> +        }
> +        generate_exception_if(!(msr_val & USER_MSR_ENABLE), X86_EXC_UD);
> +        generate_exception_if(imm1 & ~0x3fff, X86_EXC_GP, 0);
> +
> +        /* Check the corresponding bitmap. */
> +        ea.mem.off = msr_val & ~0xfff;
> +        if ( vex.pfx != vex_f2 )
> +            ea.mem.off += 0x800;
> +        ea.mem.off += imm1 >> 3;
> +        if ( (rc = ops->read(x86_seg_sys, ea.mem.off, &b, 1,
> +                             ctxt)) != X86EMUL_OKAY )
> +            goto done;
> +        generate_exception_if(!(b & (1 << (imm1 & 7))), X86_EXC_GP, 0);
> +
> +        /* Carry out the actual MSR access. */
> +        if ( vex.pfx == vex_f2 )
> +        {
> +            /* urdmsr */
> +            if ( (rc = ops->read_msr(imm1, &msr_val, ctxt)) != X86EMUL_OKAY )
> +                goto done;
> +            dst.val = msr_val;
> +            ASSERT(dst.type == OP_REG);
> +            dst.bytes = 8;
> +        }
> +        else
> +        {
> +            /* uwrmsr */
> +            switch ( imm1 )
> +            {
> +            case 0x1b00: /* UINTR_TIMER */
> +            case 0x1b01: /* UARCH_MISC_CTL */
> +                break;

These lack MSR-specific feature checks; adding the missing raising of #GP(0)
for v8.

Jan