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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v14 8/9] xen/riscv: introduce ANDN_INSN
RISC-V does a conditional toolchain for the Zbb extension
(xen/arch/riscv/rules.mk), but unconditionally uses the
ANDN instruction in emulate_xchg_1_2().
Fixes: 51dabd6312c ("xen/riscv: introduce cmpxchg.h")
Suggested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
Suggested-By: Jan Beulich <jbeulich@xxxxxxxx>
---
Andrew,
Could you please take a look if you are okay with suggested
changes.
Thanks in advance.
---
Changes in V14:
- update the commit on top of ANDN definition.
- use .insn instead of andn to support gas which doesn't understand
andn instruction.
- add Suggested-By: Jan Beulich <jbeulich@xxxxxxxx>
---
Changes in V13:
- new patch
---
xen/arch/riscv/include/asm/cmpxchg.h | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/xen/arch/riscv/include/asm/cmpxchg.h
b/xen/arch/riscv/include/asm/cmpxchg.h
index d5e678c036..34d5bd48b3 100644
--- a/xen/arch/riscv/include/asm/cmpxchg.h
+++ b/xen/arch/riscv/include/asm/cmpxchg.h
@@ -18,6 +18,19 @@
: "r" (new) \
: "memory" );
+/*
+ * To not face an issue that gas doesn't understand ANDN instruction
+ * it is encoded using .insn directive.
+ */
+#ifdef __riscv_zbb
+#define ANDN_INSN(rd, rs1, rs2) \
+ ".insn r 0x33, 0x7, 0x20, " rd ", " rs1 ", " rs2 "\n"
+#else
+#define ANDN_INSN(rd, rs1, rs2) \
+ "not " rd ", " rs2 "\n" \
+ "and " rd ", " rs1 ", " rd "\n"
+#endif
+
/*
* For LR and SC, the A extension requires that the address held in rs1 be
* naturally aligned to the size of the operand (i.e., eight-byte aligned
@@ -48,7 +61,7 @@
\
asm volatile ( \
"0: lr.w" lr_sfx " %[old], %[ptr_]\n" \
- " andn %[scratch], %[old], %[mask]\n" \
+ ANDN_INSN("%[scratch]", "%[old]", "%[mask]") \
" or %[scratch], %[scratch], %z[new_]\n" \
" sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \
" bnez %[scratch], 0b\n" \
--
2.45.2
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