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Re: [PATCH 2/3] xen/x86: address violations of MISRA C:2012 Rule 14.4


  • To: Simone Ballarin <simone.ballarin@xxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 7 Dec 2023 11:54:57 +0100
  • Autocrypt: addr=jbeulich@xxxxxxxx; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL
  • Cc: consulting@xxxxxxxxxxx, Maria Celeste Cesario <maria.celeste.cesario@xxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Thu, 07 Dec 2023 10:55:12 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 07.12.2023 10:48, Simone Ballarin wrote:
> --- a/xen/arch/x86/hpet.c
> +++ b/xen/arch/x86/hpet.c
> @@ -279,7 +279,7 @@ static int hpet_msi_write(struct hpet_event_channel *ch, 
> struct msi_msg *msg)
>  {
>      ch->msi.msg = *msg;
>  
> -    if ( iommu_intremap )
> +    if ( iommu_intremap != iommu_intremap_off )
>      {
>          int rc = iommu_update_ire_from_msi(&ch->msi, msg);
>  
> @@ -353,7 +353,7 @@ static int __init hpet_setup_msi_irq(struct 
> hpet_event_channel *ch)
>      u32 cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
>      irq_desc_t *desc = irq_to_desc(ch->msi.irq);
>  
> -    if ( iommu_intremap )
> +    if ( iommu_intremap != iommu_intremap_off )
>      {
>          ch->msi.hpet_id = hpet_blockid;
>          ret = iommu_setup_hpet_msi(&ch->msi);
> @@ -372,7 +372,7 @@ static int __init hpet_setup_msi_irq(struct 
> hpet_event_channel *ch)
>          ret = __hpet_setup_msi_irq(desc);
>      if ( ret < 0 )
>      {
> -        if ( iommu_intremap )
> +        if ( iommu_intremap != iommu_intremap_off )
>              iommu_update_ire_from_msi(&ch->msi, NULL);
>          return ret;
>      }
> diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c
> index 7f8e794254..72dce2e4ab 100644
> --- a/xen/arch/x86/msi.c
> +++ b/xen/arch/x86/msi.c
> @@ -189,7 +189,7 @@ static int write_msi_msg(struct msi_desc *entry, struct 
> msi_msg *msg)
>  {
>      entry->msg = *msg;
>  
> -    if ( iommu_intremap )
> +    if ( iommu_intremap != iommu_intremap_off )
>      {
>          int rc;
>  
> @@ -555,7 +555,7 @@ int msi_free_irq(struct msi_desc *entry)
>              destroy_irq(entry[nr].irq);
>  
>          /* Free the unused IRTE if intr remap enabled */
> -        if ( iommu_intremap )
> +        if ( iommu_intremap != iommu_intremap_off )
>              iommu_update_ire_from_msi(entry + nr, NULL);
>      }
>  

All of this would logically be part of patch 1. Is there a particular reason
why it wasn't done right there?

> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -1320,7 +1320,7 @@ x86_emulate(
>          ea.bytes = 2;
>          goto srcmem_common;
>      case SrcMem:
> -        if ( state->simd_size )
> +        if ( state->simd_size != simd_none )
>              break;
>          ea.bytes = (d & ByteOp) ? 1 : op_bytes;
>      srcmem_common:
> @@ -1460,7 +1460,7 @@ x86_emulate(
>          /* Becomes a normal DstMem operation from here on. */
>      case DstMem:
>          generate_exception_if(ea.type == OP_MEM && evex.z, X86_EXC_UD);
> -        if ( state->simd_size )
> +        if ( state->simd_size != simd_none )
>          {
>              generate_exception_if(lock_prefix, X86_EXC_UD);
>              break;
> @@ -8176,7 +8176,7 @@ x86_emulate(
>          goto done;
>      }
>  
> -    if ( state->rmw )
> +    if ( state->rmw != rmw_NONE )
>      {
>          ea.val = src.val;
>          op_bytes = dst.bytes;
> @@ -8205,7 +8205,7 @@ x86_emulate(
>  
>          dst.type = OP_NONE;
>      }
> -    else if ( state->simd_size )
> +    else if ( state->simd_size != simd_none )
>      {
>          generate_exception_if(!op_bytes, X86_EXC_UD);
>          generate_exception_if((vex.opcx && (d & TwoOp) &&

I'd be (somewhat reluctantly) okay with ack-ing this part of the patch.

Jan



 


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