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Re: [PATCH v2] x86/cpuid: enumerate and expose PREFETCHIT{0,1}
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 23 Nov 2023 08:23:38 +0100
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- Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Thu, 23 Nov 2023 07:23:54 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 22.11.2023 13:25, Andrew Cooper wrote:
> On 22/11/2023 7:43 am, Jan Beulich wrote:
>> --- a/xen/tools/gen-cpuid.py
>> +++ b/xen/tools/gen-cpuid.py
>> @@ -274,7 +274,7 @@ def crunch_numbers(state):
>> # superpages, PCID and PKU are only available in 4 level paging.
>> # NO_LMSL indicates the absense of Long Mode Segment Limits, which
>> # have been dropped in hardware.
>> - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL],
>> + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI],
>
> I know this is what the ISE says, but I'm not sure it's a legitimate
> dependency.
>
> It is an implementation detail that Intel depend on a RIP-relative
> address, but there are no architectural reason why other implementations
> couldn't make this work in 32bit too.
>
> The worst that happens without this dependency is that 32bit-only VMs
> see a hint bit about certain NOPs having uarch side effects, which
> they'll ignore for other reasons.
I'm okay either way. Adding the dependency was the only reason to have
a v2 ...
> So I recommend dropping the dependency. If you're happy, then
> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Thanks.
Jan
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