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Re: [PATCH] x86/amd: do not expose HWCR.TscFreqSel to guests
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 13 Sep 2023 15:27:18 +0200
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- Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, Wei Liu <wl@xxxxxxx>, solene@xxxxxxxxxxx, Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>, Demi Marie Obenour <demi@xxxxxxxxxxxxxxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Wed, 13 Sep 2023 13:27:27 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 13.09.2023 12:50, Andrew Cooper wrote:
> On 13/09/2023 8:50 am, Roger Pau Monné wrote:
>> Hm, there's no written down note that TSC_FREQ_SEL implies PSTATE0 to
>> be available (and PSTATE0 is not an architectural MSR), but I can see
>> how a guest can expect to fetch the P0 frequency if it sees
>> TSC_FREQ_SEL.
>
> The PPR is a reference of mostly autogenerated details and misc notes,
> put together in a non- hand-write way, unlike the older BKWGs.
>
> Lots of the information elided from public and partner-NDA versions is
> "see TICKET/LINK for rational" type comments.
>
> It is not a spec - it is a reference (the clue is even in the name)
> aimed at people already familiar with the area. Do not fall into the
> trap of thinking it it can be read as a spec.
But then where is it written down that the bit set implies the PSTATEn
MSRs to exist?
Jan
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