Re: [PATCH v6 2/2] xen/riscv: introduce identity mapping

[Oleksii <oleksii.kurochko@xxxxxxxxx>]

On Tue, 2023-08-01 at 16:50 +0200, Jan Beulich wrote:
> On 01.08.2023 16:30, Oleksii Kurochko wrote:
> > @@ -54,3 +70,17 @@ ENTRY(reset_stack)
> >  
> >          ret
> >  
> > +        .section .text.ident, "ax", %progbits
> > +
> > +ENTRY(turn_on_mmu)
> > +        sfence.vma
> > +
> > +        li      t0, RV_STAGE1_MODE
> > +        slli    t0, t0, SATP_MODE_SHIFT
> > +
> > +        la      t1, stage1_pgtbl_root
> > +        srl     t1, t1, PAGE_SHIFT
> 
> I think it would be good to be consistent in the use of pseudo insns:
> Above you use slli, so here it would want to be srli (or the other
> way around).
Oops, I overlooked that.
When I examined the disassembler, it automatically transformed it to
'srli',
so I forgot to change it.

It would be more appropriate to use 'srli'.

I'll wait for any additional comments, and if there are none, I'll send
a new patch series version.

Thanks.

~ Oleksii
> 
> > +        or      t1, t1, t0
> > +        csrw    CSR_SATP, t1
> > +
> > +        jr      a0
>