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Re: [PATCH 4/6] x86/cpu-policy: MSR_ARCH_CAPS feature names
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 16 May 2023 15:11:15 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Tue, 16 May 2023 13:11:23 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 16.05.2023 14:56, Andrew Cooper wrote:
> On 16/05/2023 1:27 pm, Jan Beulich wrote:
>> On 15.05.2023 16:42, Andrew Cooper wrote:
>>> Seed the default visibility from the dom0 special case, which for the most
>>> part just exposes the *_NO bits.
>> EIBRS and SKIP_L1DFL are outliers here, in not presently being exposed
>> to Dom0. If (latent) exposing of them wasn't an oversight, then this would
>> imo want justifying here. They'll get exposed, after all, ...
>
> EIBRS is exposed to dom0. I've intentionally renamed it from
> ARCH_CAPS_IBRS_ALL because EIBRS is by far the more recognisable name now.
Oh, of course - I should have looked at more than just the names themselves.
Hence the comment on a later patch then also is incorrectly saying "two bits",
when referring back here.
Jan
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