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Re: [PATCH v5 1/4] xen/riscv: add VM space layout


  • To: Oleksii <oleksii.kurochko@xxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Tue, 2 May 2023 08:09:36 +0200
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  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Gianluca Guida <gianluca@xxxxxxxxxxxx>, Bob Eshleman <bobbyeshleman@xxxxxxxxx>, Alistair Francis <alistair.francis@xxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>
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On 29.04.2023 12:05, Oleksii wrote:
>>>> For
>>>> RISC-V, I would recommend to make sure the struct page_info will
>>>> never
>>>> cross a cache boundary.
> Do you mean that size(struct page_info) <= cache line size?

I don't think that's what was meant. Instead I expect the goal is for no
struct page_info instance to ever cross a cache line boundary. IOW one
of sizeof(struct page_info) % cachelinesize == 0 or
cachelinesize % sizeof(struct page_info) == 0, or in yet different terms
(with the expectation that cache lines are always a power of two in size)
sizeof(struct page_info) == 2**n. Yet unless you're able to fit everything
in 32 bytes, that'll mean more overhead than strictly necessary.

Jan



 


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