[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [XEN v6 12/12] xen/arm: p2m: Enable support for 32bit IPA for ARM_32
Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx> --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. v5 - 1. Rebased on top of the changes in the previous patch. xen/arch/arm/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 1fe3cccf46..6e13772cbc 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2265,7 +2265,7 @@ void __init setup_virt_paging(void) [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ #else - [0] = { 0 }, /* Invalid */ + [0] = { 32, 0/*0*/, 0, 1 }, [1] = { 0 }, /* Invalid */ [3] = { 0 } /* Invalid */ #endif -- 2.17.1
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