[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v6 04/12] xen/arm: add SVE exception class handling
SVE has a new exception class with code 0x19, introduce the new code and handle the exception. Signed-off-by: Luca Fancellu <luca.fancellu@xxxxxxx> Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx> --- Changes from v5: - modified error messages (Julien) - add R-by Bertrand Changes from v4: - No changes Changes from v3: - No changes Changes from v2: - No changes Changes from v1: - No changes Changes from RFC: - No changes --- xen/arch/arm/include/asm/processor.h | 1 + xen/arch/arm/traps.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index bc683334125c..7e42ff8811fc 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -426,6 +426,7 @@ #define HSR_EC_HVC64 0x16 #define HSR_EC_SMC64 0x17 #define HSR_EC_SYSREG 0x18 +#define HSR_EC_SVE 0x19 #endif #define HSR_EC_INSTR_ABORT_LOWER_EL 0x20 #define HSR_EC_INSTR_ABORT_CURR_EL 0x21 diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c0611c2ef6a5..d672d2c694ef 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2173,6 +2173,11 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) perfc_incr(trap_sysreg); do_sysreg(regs, hsr); break; + case HSR_EC_SVE: + GUEST_BUG_ON(regs_mode_is_32bit(regs)); + gprintk(XENLOG_WARNING, "Domain tried to use SVE while not allowed\n"); + inject_undef_exception(regs, hsr); + break; #endif case HSR_EC_INSTR_ABORT_LOWER_EL: @@ -2202,6 +2207,10 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) case HSR_EC_BRK: do_trap_brk(regs, hsr); break; + case HSR_EC_SVE: + /* An SVE exception is a bug somewhere in hypervisor code */ + do_unexpected_trap("SVE trap at EL2", regs); + break; #endif case HSR_EC_DATA_ABORT_CURR_EL: case HSR_EC_INSTR_ABORT_CURR_EL: -- 2.34.1
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