Re: S0ix support in Xen

[Simon Gaiser <simon@xxxxxxxxxxxxxxxxxxxxxx>]

Roger Pau Monné:
> On Mon, Feb 27, 2023 at 12:48:03PM +0100, Simon Gaiser wrote:
>> Hi,
>>
>> I have been looking into using S0ix with Xen. On systems with with
>> 11th gen (Tiger Lake) Intel mobile CPUs or newer this is often the
>> only supported suspend method, thus we want to support it in Qubes
>> OS.
>>
>> Below a summary of my current understanding of what's needed (and
>> known unknowns). I would appreciate some feedback (what's missing,
>> preferred solutions, etc.).
>>
>> Note this topic is much above my previous experience with Xen and x86
>> power management internals, so sorry if I'm missing things that are
>> obvious to you.
>>
>> PIT timer: During some previous private discussion it was mentioned
>> that the PIT timer that Xen initializes for IO-APIC testing prevents
>> S0ix residency and therefore that part needs to be reworked. But if
>> I'm reading the current code correctly Xen can already use the HPET
>> timer instead, either with an automatic fallback if PIT is
>> unavailable or by forcing it via hpet=legacy-replacement=1. Looking
>> at the rest I think the PIT isn't used if Xen finds another
>> clocksource. Did I miss something?
> 
> Do you have some reference to documentation related to the S0ix
> states?
> 
> I would like to understand exactly what's required in terms of
> hardware devices the OS can use and still be able to enter such
> states.

Unfortunately the documentation that I'm aware of is rather sparse.
There are two blog posts by Intel [1] and [2] that are quite good when
you are trying to get it working under Linux. [3] might be also useful
for debugging. 

But I'm not aware of an explicit and complete list of what is required
to enter S0ix. You can deduct things from the blog posts or for example
the names of the debug register fields, but yeah ...

Also [2] contains this gem:

    Currently, only the NDA version of the Intel® SoC Watch tool can
    expose the IP Link Power State. [...] If you have any questions,
    please refer to your Intel representative.

Regarding what devices are active in S0ix the PCH datasheet [4] has a
few additional pointers like:

    USB 3.2 only works in S0. USB 2.0 survives S0ix and Sx states and
    provides early boot access.

If someone knows about more public docs, I'm all ear.

Simon

[1]: https://01.org/blogs/qwang59/2018/how-achieve-s0ix-states-linux
[2]: https://01.org/blogs/qwang59/2020/linux-s0ix-troubleshooting
[3]: 
https://01.org/blogs/2019/using-power-management-controller-drivers-debug-low-power-platform-states
[4]: https://cdrdv2.intel.com/v1/dl/getContent/631119

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