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Re: [XEN v2 11/11] xen/arm: p2m: Enable support for 32bit IPA
- To: Julien Grall <julien@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Tue, 7 Feb 2023 15:34:56 +0000
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On 20/01/2023 11:06, Julien Grall wrote:
Hi Ayan,
Hi Julien,
On 17/01/2023 17:43, Ayan Kumar Halder wrote:
VTCR.T0SZ should be set as 0x20 to support 32bit IPA.
Refer ARM DDI 0487I.a ID081822, G8-9824, G8.2.171, VTCR,
"Virtualization Translation Control Register" for the bit descriptions.
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
---
Changes from -
v1 - New patch.
xen/arch/arm/p2m.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index 948f199d84..cfdea55e71 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -2266,13 +2266,17 @@ void __init setup_virt_paging(void)
register_t val =
VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA;
#ifdef CONFIG_ARM_32
- if ( p2m_ipa_bits < 40 )
+ if ( p2m_ipa_bits < PADDR_BITS )
panic("P2M: Not able to support %u-bit IPA at the moment\n",
p2m_ipa_bits);
- printk("P2M: 40-bit IPA\n");
- p2m_ipa_bits = 40;
+ printk("P2M: %u-bit IPA\n",PADDR_BITS);
+ p2m_ipa_bits = PADDR_BITS;
+#ifdef CONFIG_ARM_PA_32
+ val |= VTCR_T0SZ(0x20); /* 32 bit IPA */
+#else
val |= VTCR_T0SZ(0x18); /* 40 bit IPA */
+#endif
I am wondering whether this is right time to switch to an array like
the arm64 code? This would allow to use 32-bit IPA also when Xen
support 64-bit physical address.
In AArch64, we use ID_AA64MMFR0_EL1.PARange to determine the physical
address range supported at runtime. This is then used as an index into
pa_range_info[] to determine t0sz, root_order, etc.
However, for AArch32 I do not see an equivalent register (similar to
ID_AA64MMFR0_EL1) or any register to determine the physical address
range. Thus, I will prefer to keep the code as it is unless you suggest
any alternative.
- Ayan
Cheers,
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