[PATCH v3 01/14] xen/riscv: change ISA to r64G

[Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>]

Work with some registers requires csr command which is part of
Zicsr.

Also ISA was changed from r64ima to r64g where G is represented the
“IMAFDZicsr Zifencei” base and extensions so basically it is the same
as it was before plus additional extensions we will need in the
nearest future.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
---
Changes in V3:
  - Change the name of config RISCV_ISA_RV64IMA to RISCV_ISA_RV64G as
    instructions from Zicsr and Zifencei extensions aren't part of I
        extension any more.
---
Changes in V2:
  - Nothing changed
---
 xen/arch/riscv/Kconfig | 14 +++++++++-----
 xen/arch/riscv/arch.mk |  2 +-
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig
index 468e250c86..f382b36f6c 100644
--- a/xen/arch/riscv/Kconfig
+++ b/xen/arch/riscv/Kconfig
@@ -19,15 +19,19 @@ menu "ISA Selection"
 
 choice
        prompt "Base ISA"
-       default RISCV_ISA_RV64IMA if RISCV_64
+       default RISCV_ISA_RV64G if RISCV_64
        help
          This selects the base ISA extensions that Xen will target.
 
-config RISCV_ISA_RV64IMA
-       bool "RV64IMA"
+config RISCV_ISA_RV64G
+       bool "RV64G"
        help
-         Use the RV64I base ISA, plus the "M" and "A" extensions
-         for integer multiply/divide and atomic instructions, respectively.
+         Use the RV64I base ISA, plus
+         "M" for multiply/divide,
+         "A" for atomic instructions,
+         “F”/"D" for  {single/double}-precision floating-point instructions,
+         "Zicsr" for control and status register access,
+         "Zifencei" for instruction-fetch fence.
 
 endchoice
 
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 012dc677c3..45fe858ee0 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -3,7 +3,7 @@
 
 CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64
 
-riscv-march-$(CONFIG_RISCV_ISA_RV64IMA) := rv64ima
+riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g
 riscv-march-$(CONFIG_RISCV_ISA_C)       := $(riscv-march-y)c
 
 # Note that -mcmodel=medany is used so that Xen can be mapped
-- 
2.39.0