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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v1 07/14] xen/riscv: introduce exception handlers implementation
On Sat, Jan 21, 2023 at 1:00 AM Oleksii Kurochko
<oleksii.kurochko@xxxxxxxxx> wrote:
>
> The patch introduces an implementation of basic exception handlers:
> - to save/restore context
> - to handle an exception itself. The handler calls wait_for_interrupt
> now, nothing more.
>
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
Alistair
> ---
> xen/arch/riscv/Makefile | 2 +
> xen/arch/riscv/entry.S | 97 ++++++++++++++++++++++++++++++
> xen/arch/riscv/include/asm/traps.h | 13 ++++
> xen/arch/riscv/traps.c | 13 ++++
> 4 files changed, 125 insertions(+)
> create mode 100644 xen/arch/riscv/entry.S
> create mode 100644 xen/arch/riscv/include/asm/traps.h
> create mode 100644 xen/arch/riscv/traps.c
>
> diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile
> index 1a4f1a6015..443f6bf15f 100644
> --- a/xen/arch/riscv/Makefile
> +++ b/xen/arch/riscv/Makefile
> @@ -1,7 +1,9 @@
> obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
> +obj-y += entry.o
> obj-$(CONFIG_RISCV_64) += riscv64/
> obj-y += sbi.o
> obj-y += setup.o
> +obj-y += traps.o
>
> $(TARGET): $(TARGET)-syms
> $(OBJCOPY) -O binary -S $< $@
> diff --git a/xen/arch/riscv/entry.S b/xen/arch/riscv/entry.S
> new file mode 100644
> index 0000000000..f7d46f42bb
> --- /dev/null
> +++ b/xen/arch/riscv/entry.S
> @@ -0,0 +1,97 @@
> +#include <asm/asm.h>
> +#include <asm/processor.h>
> +#include <asm/riscv_encoding.h>
> +#include <asm/traps.h>
> +
> + .global handle_exception
> + .align 4
> +
> +handle_exception:
> +
> + /* Exceptions from xen */
> +save_to_stack:
> + /* Save context to stack */
> + REG_S sp, (RISCV_CPU_USER_REGS_OFFSET(sp) -
> RISCV_CPU_USER_REGS_SIZE) (sp)
> + addi sp, sp, -RISCV_CPU_USER_REGS_SIZE
> + REG_S t0, RISCV_CPU_USER_REGS_OFFSET(t0)(sp)
> + j save_context
> +
> +save_context:
> + /* Save registers */
> + REG_S ra, RISCV_CPU_USER_REGS_OFFSET(ra)(sp)
> + REG_S gp, RISCV_CPU_USER_REGS_OFFSET(gp)(sp)
> + REG_S t1, RISCV_CPU_USER_REGS_OFFSET(t1)(sp)
> + REG_S t2, RISCV_CPU_USER_REGS_OFFSET(t2)(sp)
> + REG_S s0, RISCV_CPU_USER_REGS_OFFSET(s0)(sp)
> + REG_S s1, RISCV_CPU_USER_REGS_OFFSET(s1)(sp)
> + REG_S a0, RISCV_CPU_USER_REGS_OFFSET(a0)(sp)
> + REG_S a1, RISCV_CPU_USER_REGS_OFFSET(a1)(sp)
> + REG_S a2, RISCV_CPU_USER_REGS_OFFSET(a2)(sp)
> + REG_S a3, RISCV_CPU_USER_REGS_OFFSET(a3)(sp)
> + REG_S a4, RISCV_CPU_USER_REGS_OFFSET(a4)(sp)
> + REG_S a5, RISCV_CPU_USER_REGS_OFFSET(a5)(sp)
> + REG_S a6, RISCV_CPU_USER_REGS_OFFSET(a6)(sp)
> + REG_S a7, RISCV_CPU_USER_REGS_OFFSET(a7)(sp)
> + REG_S s2, RISCV_CPU_USER_REGS_OFFSET(s2)(sp)
> + REG_S s3, RISCV_CPU_USER_REGS_OFFSET(s3)(sp)
> + REG_S s4, RISCV_CPU_USER_REGS_OFFSET(s4)(sp)
> + REG_S s5, RISCV_CPU_USER_REGS_OFFSET(s5)(sp)
> + REG_S s6, RISCV_CPU_USER_REGS_OFFSET(s6)(sp)
> + REG_S s7, RISCV_CPU_USER_REGS_OFFSET(s7)(sp)
> + REG_S s8, RISCV_CPU_USER_REGS_OFFSET(s8)(sp)
> + REG_S s9, RISCV_CPU_USER_REGS_OFFSET(s9)(sp)
> + REG_S s10, RISCV_CPU_USER_REGS_OFFSET(s10)(sp)
> + REG_S s11, RISCV_CPU_USER_REGS_OFFSET(s11)(sp)
> + REG_S t3, RISCV_CPU_USER_REGS_OFFSET(t3)(sp)
> + REG_S t4, RISCV_CPU_USER_REGS_OFFSET(t4)(sp)
> + REG_S t5, RISCV_CPU_USER_REGS_OFFSET(t5)(sp)
> + REG_S t6, RISCV_CPU_USER_REGS_OFFSET(t6)(sp)
> + csrr t0, CSR_SEPC
> + REG_S t0, RISCV_CPU_USER_REGS_OFFSET(sepc)(sp)
> + csrr t0, CSR_SSTATUS
> + REG_S t0, RISCV_CPU_USER_REGS_OFFSET(sstatus)(sp)
> +
> + mv a0, sp
> + jal __handle_exception
> +
> +restore_registers:
> + /* Restore stack_cpu_regs */
> + REG_L t0, RISCV_CPU_USER_REGS_OFFSET(sepc)(sp)
> + csrw CSR_SEPC, t0
> + REG_L t0, RISCV_CPU_USER_REGS_OFFSET(sstatus)(sp)
> + csrw CSR_SSTATUS, t0
> +
> + REG_L ra, RISCV_CPU_USER_REGS_OFFSET(ra)(sp)
> + REG_L gp, RISCV_CPU_USER_REGS_OFFSET(gp)(sp)
> + REG_L t0, RISCV_CPU_USER_REGS_OFFSET(t0)(sp)
> + REG_L t1, RISCV_CPU_USER_REGS_OFFSET(t1)(sp)
> + REG_L t2, RISCV_CPU_USER_REGS_OFFSET(t2)(sp)
> + REG_L s0, RISCV_CPU_USER_REGS_OFFSET(s0)(sp)
> + REG_L s1, RISCV_CPU_USER_REGS_OFFSET(s1)(sp)
> + REG_L a0, RISCV_CPU_USER_REGS_OFFSET(a0)(sp)
> + REG_L a1, RISCV_CPU_USER_REGS_OFFSET(a1)(sp)
> + REG_L a2, RISCV_CPU_USER_REGS_OFFSET(a2)(sp)
> + REG_L a3, RISCV_CPU_USER_REGS_OFFSET(a3)(sp)
> + REG_L a4, RISCV_CPU_USER_REGS_OFFSET(a4)(sp)
> + REG_L a5, RISCV_CPU_USER_REGS_OFFSET(a5)(sp)
> + REG_L a6, RISCV_CPU_USER_REGS_OFFSET(a6)(sp)
> + REG_L a7, RISCV_CPU_USER_REGS_OFFSET(a7)(sp)
> + REG_L s2, RISCV_CPU_USER_REGS_OFFSET(s2)(sp)
> + REG_L s3, RISCV_CPU_USER_REGS_OFFSET(s3)(sp)
> + REG_L s4, RISCV_CPU_USER_REGS_OFFSET(s4)(sp)
> + REG_L s5, RISCV_CPU_USER_REGS_OFFSET(s5)(sp)
> + REG_L s6, RISCV_CPU_USER_REGS_OFFSET(s6)(sp)
> + REG_L s7, RISCV_CPU_USER_REGS_OFFSET(s7)(sp)
> + REG_L s8, RISCV_CPU_USER_REGS_OFFSET(s8)(sp)
> + REG_L s9, RISCV_CPU_USER_REGS_OFFSET(s9)(sp)
> + REG_L s10, RISCV_CPU_USER_REGS_OFFSET(s10)(sp)
> + REG_L s11, RISCV_CPU_USER_REGS_OFFSET(s11)(sp)
> + REG_L t3, RISCV_CPU_USER_REGS_OFFSET(t3)(sp)
> + REG_L t4, RISCV_CPU_USER_REGS_OFFSET(t4)(sp)
> + REG_L t5, RISCV_CPU_USER_REGS_OFFSET(t5)(sp)
> + REG_L t6, RISCV_CPU_USER_REGS_OFFSET(t6)(sp)
> +
> + /* Restore sp */
> + REG_L sp, RISCV_CPU_USER_REGS_OFFSET(sp)(sp)
> +
> + sret
> diff --git a/xen/arch/riscv/include/asm/traps.h
> b/xen/arch/riscv/include/asm/traps.h
> new file mode 100644
> index 0000000000..816ab1178a
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/traps.h
> @@ -0,0 +1,13 @@
> +#ifndef __ASM_TRAPS_H__
> +#define __ASM_TRAPS_H__
> +
> +#include <asm/processor.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +void __handle_exception(struct cpu_user_regs *cpu_regs);
> +void handle_exception(void);
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* __ASM_TRAPS_H__ */
> diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c
> new file mode 100644
> index 0000000000..3201b851ef
> --- /dev/null
> +++ b/xen/arch/riscv/traps.c
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (C) 2023 Vates
> + *
> + * RISC-V Trap handlers
> + */
> +#include <asm/processor.h>
> +#include <asm/traps.h>
> +
> +void __handle_exception(struct cpu_user_regs *cpu_regs)
> +{
> + wait_for_interrupt();
> +}
> --
> 2.39.0
>
>
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