Re: [XEN v5 10/11] xen/Arm: GICv3: Define macros to read/write 64 bit

[Julien Grall <julien@xxxxxxx>]

Hi,

On 05/12/2022 13:26, Ayan Kumar Halder wrote:
> On AArch32, ldrd/strd instructions are not atomic when used to access MMIO.
> Furthermore, ldrd/strd instructions are not decoded by Arm when running as
> a guest to access emulated MMIO region.
> Thus, we have defined readq_relaxed_non_atomic()/writeq_relaxed_non_atomic()
> which in turn calls readl_relaxed()/writel_relaxed() for the lower and upper
> 32 bits.
> For AArch64, readq_relaxed_non_atomic()/writeq_relaxed_non_atomic() invokes
> readq_relaxed()/writeq_relaxed() respectively.
> As GICv3 registers (GICD_IROUTER, GICR_TYPER) can be accessed in a non atomic
> manner, so we have used readq_relaxed_non_atomic()/readq_relaxed_non_atomic().
>
> However, the following points are noted for the non atomic access :-
> 1. In gicv3_dist_init(), using non atomic write on GICD_IROUTER is fine as this
> gets invoked when interrupts are disabled.
> 2. In gicv3_populate_rdist(), using non atomic read on GICR_TYPER is fine as
> the register is read and the interrupts are disabled as well.
> 3. In gicv3_irq_set_affinity(), using non atomic write on GICD_IROUTER. This
> may be called with interrupts enabled. So, a non-atomic access (on AArch32)
> means the GIC will see a transient value when only one of two 32-bit will be
> updated. However, only AFF3 is defined in the upper 32 bits and they are 0, so
> this will never change.
> On AArch64, writeq_relaxed_non_atomic() invokes writeq_relaxed() (which is
> atomic), so this problem does not arise.
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
Acked-by: Julien Grall <jgrall@xxxxxxxxxx>

Cheers,

--
Julien Grall