[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [XEN v3 03/12] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32
- To: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Michal Orzel <michal.orzel@xxxxxxx>
- Date: Thu, 17 Nov 2022 14:11:30 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kArmuR4bkKjuBcxB9hMbzYDZ5JaDT15JSnR6qov3KQk=; b=OJUrLA8Q3WtFfxUo7yh3TXi/aCVB45BBCvk3qavtynyRFVekhLLXyeO7bvVVaFSWramEM8Ht1OX3LvD78SY4vr92BaXywOBFO/bqWNgBqDNcEBaOWfpIKcxc4HjLMuGBJurSjTK3UVUBVnzbMuOoQvdzVB7j8evoz3PxB0rdFCF4hxl9bI0PJw32W442oalasQSw9ynlCyVhHSZCcKPGEmTgC2KxAO4Wu0OEjhwG0p2y0YBoBY9ZIaI4mOA9pbSnjhMWvC1/UjnYjcJRbO69ZGdnXCD0ASNlWPTpVyfpF0LCUGE1lLqRqHWWQiqAhzDFyLq2sDXnRjUBY1QWn3kDHg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JSehw+2Ba7klzG5TMNU8jooxQ4HtjGJCGgPYBmA2OUsTFF4ulC4vF6mTX1UO2A5t3xdbhGdC1Zp3FoTBR85/Q6fp5Oq8MIlTKUWHaLRAZOY1rNA08pmvkqX9ppjmYE9EL2koElJGPD2K9wCQL3RbvUnIM+LEEX5XBj1OGtW7FGLLRLsNqiIXwqVLKHbrahZzHKqYD2o4Kcv+DPKbW9BRkCm70traNRnSCsvg5JHrM5JVhmUPd7tFTXUNDVtGL8bIAY5RTcxbVOIqEf0s8F10G8ThAYvr3NO967ni13p6jNSeqB8qbbJ+5Hnfn9gbe28Q5dePdAhzULIIoXJmPpALzw==
- Cc: <sstabellini@xxxxxxxxxx>, <stefanos@xxxxxxxxxx>, <julien@xxxxxxx>, <Volodymyr_Babchuk@xxxxxxxx>, <bertrand.marquis@xxxxxxx>, <jgrall@xxxxxxxxxx>, <burzalodowa@xxxxxxxxx>
- Delivery-date: Thu, 17 Nov 2022 13:12:01 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hi Ayan,
On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> In some situations (e.g. GICR_TYPER), the hypervior may need to emulate
> 64bit registers in AArch32 mode. In such situations, the hypervisor may
> need to read/modify the lower or upper 32 bits of the 64 bit register.
>
> In AArch32, 'unsigned long' is 32 bits. Thus, we cannot use it for 64 bit
> registers.
>
> While we could replace 'unsigned long' by 'uint64_t', it is not entirely clear
> whether a 32-bit compiler would not allocate register for the upper 32-bit.
> Therefore fold vreg_reg_* helper in the size specific one and use the
> appropriate type based on the size requested.
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
~Michal
|