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Re: [PATCH for-4.17 v2] hvm/apic: repurpose the reporting of the APIC assist options
- To: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Fri, 11 Nov 2022 08:45:41 +0100
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- Cc: "Henry.Wang@xxxxxxx" <Henry.Wang@xxxxxxx>, Paul Durrant <paul@xxxxxxx>, Wei Liu <wl@xxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Fri, 11 Nov 2022 07:46:07 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 10.11.2022 23:47, Andrew Cooper wrote:
> On 04/11/2022 16:18, Roger Pau Monne wrote:
>> --- a/xen/arch/x86/hvm/viridian/viridian.c
>> +++ b/xen/arch/x86/hvm/viridian/viridian.c
>> @@ -197,7 +197,7 @@ void cpuid_viridian_leaves(const struct vcpu *v,
>> uint32_t leaf,
>> res->a = CPUID4A_RELAX_TIMER_INT;
>> if ( viridian_feature_mask(d) & HVMPV_hcall_remote_tlb_flush )
>> res->a |= CPUID4A_HCALL_REMOTE_TLB_FLUSH;
>> - if ( !cpu_has_vmx_apic_reg_virt )
>> + if ( !has_assisted_xapic(d) )
>> res->a |= CPUID4A_MSR_BASED_APIC;
>
> This check is broken before and after. It needs to be keyed on
> virtualised interrupt delivery, not register acceleration.
To me this connection you suggest looks entirely unobvious, so would
you mind expanding as to why you're thinking so? The hint to the guest
here is related to how it would best access certain registers (aiui),
which to me looks orthogonal to how interrupt delivery works.
Jan
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