[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN v2 02/12] xen/Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32


  • To: Ayan Kumar Halder <ayankuma@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Michal Orzel <michal.orzel@xxxxxxx>
  • Date: Tue, 1 Nov 2022 09:58:18 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ihZ6D3XwiQaBzze2onm8m0Z/6iwE3d4+vSCAl91VIEo=; b=OOQulLRqrRDfwKAu4AxnH+PM8/98pHjdurxVQ8wBxdGdjkkMmDZ2ZNXNZWWupjlS+xKdVmyZw6kwBtFlTzE0ef6z/IVJ5Fhl1c03ZtpiwdNwALPra/n+5bgUZfixMXypBoNqgXyL01P3g6mmCHa4mobxbCmfUK5Fr5ALJupkOvmY1bKFcGGSfTbtz4WfpDktZyOEMBBQ4l/wB5uzROJRt6ssEhsf8TQsIUtSaaq33BClFPYg26CrMSG/ocwHv3tb5ItIzFkD6CXRX/k08bZOCQrOrVqRlwZu1xYo6oj7T1eBEPO1UG8opO7tqpJ+Y+aquWVLBdUEc6QxIVbjgETUzg==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JauM+JLftHdMKWSjuM7HxcIocdigQYqt80qduB5yjvYmEza5maZMrcvbaDuJhdOScXRuZ/moDUP4wZf5dWFcWCvKAoHPmJ4HhrqDBNlFkRV5TVjukDhy8EBss/Q61H40DGO2UIXy/H+f/dkc/8DQfl2FHXFgtn0Ym8UWGSzSlX+s6RWLqFB9D//GJnwY5wg3jhw9FXiyT+6viuOzMeguQSxoDE0EtDBlG3pVa52eNG2eX0iHRJwamJQTaGyrsqoI8bBJMfgiEHC1BgLt9u3nns2OGk+bRh0vm8OH8K7AmcJKvdxZFwMl4sptkpPe10tt2P+IpNrxLYg+45g4gQBowg==
  • Cc: <sstabellini@xxxxxxxxxx>, <stefanos@xxxxxxxxxx>, <julien@xxxxxxx>, <Volodymyr_Babchuk@xxxxxxxx>, <bertrand.marquis@xxxxxxx>, <burzalodowa@xxxxxxxxx>
  • Delivery-date: Tue, 01 Nov 2022 08:58:49 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>


On 31/10/2022 18:53, Michal Orzel wrote:
> 
> 
> Hi Ayan,
> 
> On 31/10/2022 16:13, Ayan Kumar Halder wrote:
>>
>>
>> Refer 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv6.1-rc1%2Fsource%2Farch%2Farm64%2F&amp;data=05%7C01%7Cmichal.orzel%40amd.com%7C0b2a0d1537104c2391d008dabb68eabb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638028356554609284%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=RhhL0XWxLJsO7vsP0DoP1QMvUMwGV%2F4FPJwAyvStj4k%3D&amp;reserved=0
>>  \
> You should not split the link as it is becoming unusable in that form.
> 
>> include/asm/cputype.h#L14 , for the macros specific for arm64.
>>
>> Refer 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv6.1-rc1%2Fsource%2Farch%2Farm%2Finclude%2F&amp;data=05%7C01%7Cmichal.orzel%40amd.com%7C0b2a0d1537104c2391d008dabb68eabb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638028356554609284%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=gLsNWm5%2BSyy51rn%2BA6H8PrWg8Yv%2BERicyyDjshOd3hc%3D&amp;reserved=0
>>  \
> Same here.
> 
>> asm/cputype.h#L54  , for the macros specific for arm32.
>>
>> MPIDR_LEVEL_SHIFT() differs between 64 and 32 bit.
>> For 64 bit :-
>>
>>  aff_lev3          aff_lev2 aff_lev1 aff_lev0
>> |________|________|________|________|________|
>> 40       32       24       16       8        0
>>
>> For 32 bit :-
>>
>>  aff_lev3 aff_lev2 aff_lev1 aff_lev0
>> |________|________|________|________|
>> 32       24       16       8        0
>>
> 
> Where did you get this info from?
> FWICS by looking at ARM ARM DDI 0487I.a D17-6118,
> "Aff3 is not supported in AArch32 state."
We're talking about arm32 and not AArch32. My bad.
Nevertheless, looking at ARM ARM DDI 0406C.d B4-1644,
MPIDR for Armv7A/R also does not have aff3.

> 
> 
>> Signed-off-by: Ayan Kumar Halder <ayankuma@xxxxxxx>
>> ---
>>
>> Changes from :-
>> v1 - 1. Rearranged the macro defines so that the common code (between arm32
>> and arm64) is placed in "arm/include/asm/processor.h".
>>
>>  xen/arch/arm/include/asm/arm32/processor.h | 5 +++++
>>  xen/arch/arm/include/asm/arm64/processor.h | 8 ++++++++
>>  xen/arch/arm/include/asm/processor.h       | 6 ------
>>  3 files changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/xen/arch/arm/include/asm/arm32/processor.h 
>> b/xen/arch/arm/include/asm/arm32/processor.h
>> index 4e679f3273..82aa7f8d9d 100644
>> --- a/xen/arch/arm/include/asm/arm32/processor.h
>> +++ b/xen/arch/arm/include/asm/arm32/processor.h
>> @@ -56,6 +56,11 @@ struct cpu_user_regs
>>      uint32_t pad1; /* Doubleword-align the user half of the frame */
>>  };
>>
>> +/*
>> + * Macros to extract affinity level. Picked from kernel
>> + */
> No need for a multiline comment here and everywhere else.
> 
>> +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * (level))
>> +
>>  #endif
>>
>>  #endif /* __ASM_ARM_ARM32_PROCESSOR_H */
>> diff --git a/xen/arch/arm/include/asm/arm64/processor.h 
>> b/xen/arch/arm/include/asm/arm64/processor.h
>> index c749f80ad9..295483a9dd 100644
>> --- a/xen/arch/arm/include/asm/arm64/processor.h
>> +++ b/xen/arch/arm/include/asm/arm64/processor.h
>> @@ -84,6 +84,14 @@ struct cpu_user_regs
>>      uint64_t sp_el1, elr_el1;
>>  };
>>
>> +/*
>> + * Macros to extract affinity level. picked from kernel
>> + */
>> +#define MPIDR_LEVEL_BITS_SHIFT  3
>> +
>> +#define MPIDR_LEVEL_SHIFT(level) \
>> +         (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
>> +
> You should move these macros below __DECL_REG as they do not require having 
> it defined.
> 
>>  #undef __DECL_REG
>>
>>  #endif /* __ASSEMBLY__ */
>> diff --git a/xen/arch/arm/include/asm/processor.h 
>> b/xen/arch/arm/include/asm/processor.h
>> index 1dd81d7d52..ecfb62bbbe 100644
>> --- a/xen/arch/arm/include/asm/processor.h
>> +++ b/xen/arch/arm/include/asm/processor.h
>> @@ -122,13 +122,7 @@
>>  /*
>>   * Macros to extract affinity level. picked from kernel
>>   */
>> -
>> -#define MPIDR_LEVEL_BITS_SHIFT  3
>>  #define MPIDR_LEVEL_MASK        ((1 << MPIDR_LEVEL_BITS) - 1)
>> -
>> -#define MPIDR_LEVEL_SHIFT(level) \
>> -         (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
>> -
>>  #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
>>           (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
>>
>> --
>> 2.17.1
>>
>>
> 
> ~Michal
> 



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.