Re: [RFC PATCH v1 08/12] Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32

[Julien Grall <julien@xxxxxxx>]

Hi Ayan,

On 21/10/2022 16:31, Ayan Kumar Halder wrote:
> Refer "Arm IHI 0069H ID020922",
> 12.7.1 - Interrupt Controller Hyp Active Priorities Group0 Registers 0-3
> 12.7.2 - Interrupt Controller Hyp Active Priorities Group1 Registers 0-3
>
> Signed-off-by: Ayan Kumar Halder <ayankuma@xxxxxxx>
> ---
>   xen/arch/arm/include/asm/arm32/sysregs.h | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h 
> b/xen/arch/arm/include/asm/arm32/sysregs.h
> index f3b4dfbca8..693da22324 100644
> --- a/xen/arch/arm/include/asm/arm32/sysregs.h
> +++ b/xen/arch/arm/include/asm/arm32/sysregs.h
As the previous patch, the define should be declared in cpregs.h.

> @@ -117,6 +117,18 @@
>   #define ICH_LRC14_EL2              __LRC8_EL2(6)
>   #define ICH_LRC15_EL2              __LRC8_EL2(7)
>   
> +#define __AP0Rx_EL2(x)            ___CP32(p15,4,c12,c8,x)
> +#define ICH_AP0R0_EL2             __AP0Rx_EL2(0)
> +#define ICH_AP0R1_EL2             __AP0Rx_EL2(1)
> +#define ICH_AP0R2_EL2             __AP0Rx_EL2(2)
> +#define ICH_AP0R3_EL2             __AP0Rx_EL2(3)
> +
> +#define __AP1Rx_EL2(x)            ___CP32(p15,4,c12,c9,x)
> +#define ICH_AP1R0_EL2             __AP1Rx_EL2(0)
> +#define ICH_AP1R1_EL2             __AP1Rx_EL2(1)
> +#define ICH_AP1R2_EL2             __AP1Rx_EL2(2)
> +#define ICH_AP1R3_EL2             __AP1Rx_EL2(3)
> +
>   #endif /* __ASSEMBLY__ */
>   
>   #endif /* __ASM_ARM_ARM32_SYSREGS_H */
Cheers,

--
Julien Grall