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Re: [PATCH v2] x86/PV: issue branch prediction barrier when switching 64-bit guest to kernel mode
- To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 13 Sep 2022 18:05:30 +0200
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Tue, 13 Sep 2022 16:05:46 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 13.09.2022 17:41, Roger Pau Monné wrote:
> On Tue, Jul 19, 2022 at 02:55:17PM +0200, Jan Beulich wrote:
>> Since both kernel and user mode run in ring 3, they run in the same
>> "predictor mode". While the kernel could take care of this itself, doing
>> so would be yet another item distinguishing PV from native. Additionally
>> we're in a much better position to issue the barrier command, and we can
>> save a #GP (for privileged instruction emulation) this way.
>>
>> To allow to recover performance, introduce a new VM assist allowing the guest
>> kernel to suppress this barrier.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>> ---
>> v2: Leverage entry-IBPB. Add VM assist. Re-base.
>> ---
>> I'm not entirely happy with re-using opt_ibpb_ctxt_switch here (it's a
>> mode switch after all, but v1 used opt_ibpb here), but it also didn't
>> seem very reasonable to introduce yet another command line option. The
>> only feasible alternative I would see is to check the CPUID bits directly.
>
> Likely needs a mention in xen-command-line.md that the `ibpb` option
> also controls whether a barrier is executed by Xen in PV vCPU context
> switches from user-space to kernel. The current text only mentions
> vCPU context switches.
Andrew and I actually discussed this perhaps better having a separate
control.
Jan
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