Re: [PATCH] xen/arm: gic: Fix MISRA C 2012 Rule 20.7 violation

[Julien Grall <julien@xxxxxxx>]

Hi Xenia,

Thank for your effort to make Xen MISRA compliant. Personally, I find 
quite difficult to follow what's going on with dozen of single patches.
It is also makes more difficult for a committer to apply them. For 
instance, tools like 'b4' can easily apply a series. So there are less 
effort required.
So would you be able to try to batch your patches in larger series 
(maybe 10-20 patches)?
Cheers,

On 10/08/2022 11:15, Xenia Ragiadakou wrote:
> In GIC_PRI_TO_GUEST(), add parentheses around the macro parameter 'pri' to
> prevent against unintended expansions and realign comment.
>
> Signed-off-by: Xenia Ragiadakou <burzalodowa@xxxxxxxxx>
> ---
>   xen/arch/arm/include/asm/gic.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
> index b3c6c67933..3692fae393 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -152,8 +152,8 @@
>   #define GIC_PRI_IPI_ALL    ((GIC_PRI_IPI << 24) | (GIC_PRI_IPI << 16) |\
>                               (GIC_PRI_IPI << 8) | GIC_PRI_IPI)
>   
> -#define GIC_PRI_TO_GUEST(pri) (pri >> 3) /* GICH_LR and GICH_VMCR only support
> -                                            5 bits for guest irq priority */
> +#define GIC_PRI_TO_GUEST(pri) ((pri) >> 3) /* GICH_LR and GICH_VMCR only 
> support
> +                                              5 bits for guest irq priority */
>   
>   #define GICH_LR_PENDING         1
>   #define GICH_LR_ACTIVE          2
--
Julien Grall