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Re: [PATCH v2] x86/msr: fix X2APIC_LAST
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- Date: Wed, 27 Jul 2022 10:56:47 +0000
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- Cc: Jun Nakajima <jun.nakajima@xxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Edwin Torok <edvin.torok@xxxxxxxxxx>
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH v2] x86/msr: fix X2APIC_LAST
On 26/07/2022 16:47, Jan Beulich wrote:
> On 26.07.2022 17:42, Andrew Cooper wrote:
>> On 26/07/2022 16:33, Jan Beulich wrote:
>>> On 26.07.2022 17:28, Edwin Török wrote:
>>>> The latest Intel manual now says the X2APIC reserved range is only
>>>> 0x800 to 0x8ff (NOT 0xbff).
>>>> This changed between SDM 68 (Nov 2018) and SDM 69 (Jan 2019).
>>>> The AMD manual documents 0x800-0x8ff too.
>>>>
>>>> There are non-X2APIC MSRs in the 0x900-0xbff range now:
>>>> e.g. 0x981 is IA32_TME_CAPABILITY, an architectural MSR.
>>>>
>>>> The new MSR in this range appears to have been introduced in Icelake,
>>>> so this commit should be backported to Xen versions supporting Icelake.
>>>>
>>>> Backport: 4.13+
>>> FAOD nevertheless it'll be applied only back to 4.15.
>> It shouldn't go back before 4.16, because otherwise we start exposing a
>> bunch of MSRs (including undocumented ones on Haswell/Broadwell) which
>> were previously disallowed.
> Hmm, I'm confused - how would the limiting of this range cause more
> MSRs to be exposed in 4.15?
My mistake. I forgot when we changed the MSR default readability.
This should go back to 4.15.
~Andrew
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