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Re: [PATCH] x86/msr: fix X2APIC_LAST
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Edwin Torok <edvin.torok@xxxxxxxxxx>
- Date: Tue, 26 Jul 2022 15:29:55 +0000
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- Cc: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
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- Thread-topic: [PATCH] x86/msr: fix X2APIC_LAST
> On 26 Jul 2022, at 16:07, Jan Beulich <jbeulich@xxxxxxxx> wrote:
>
> On 26.07.2022 16:43, Edwin Török wrote:
>> --- a/xen/arch/x86/include/asm/msr-index.h
>> +++ b/xen/arch/x86/include/asm/msr-index.h
>> @@ -148,7 +148,7 @@
>> #define MSR_INTERRUPT_SSP_TABLE 0x000006a8
>>
>> #define MSR_X2APIC_FIRST 0x00000800
>> -#define MSR_X2APIC_LAST 0x00000bff
>> +#define MSR_X2APIC_LAST 0x000008ff
>
> May I ask that then the now open-coded values of MSR_X2APIC_LAST
> (two instances in vmx.c using MSR_X2APIC_FIRST + 0xff) be replaced
> at the same time?
> On 26 Jul 2022, at 16:03, Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx> wrote:
>
> On 26/07/2022 15:43, Edwin Török wrote:
>> The latest Intel manual now says the X2APIC reserved range is only
>> 0x800 to 0x8ff (NOT 0xbff). The AMD manual documents 0x800-0x8ff too.
>>
>> There are non-X2APIC MSRs in the 0x900-0xbff range now:
>> e.g. 0x981 is IA32_TME_CAPABILITY, an architectural MSR.
>>
>> The new MSR in this range appears to have been introduced in Icelake,
>> so this commit should be backported to Xen versions supporting Icelake.
>>
>> Backport: 4.13+
>>
>> Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx>
>
> Having done some archaeology, this changed between SDM 68 (Nov 2018) and
> SDM 69 (Jan 2019)
Thanks, I've done both of these updates in the v2 I've sent out.
Best regards,
--Edwin
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