Re: [PATCH v7 05/14] AMD/IOMMU: allow use of superpage mappings

["Durrant, Paul" <xadimgnik@xxxxxxxxx>]

On 05/07/2022 13:45, Jan Beulich wrote:
> No separate feature flags exist which would control availability of
> these; the only restriction is HATS (establishing the maximum number of
> page table levels in general), and even that has a lower bound of 4.
> Thus we can unconditionally announce 2M and 1G mappings. (Via non-
> default page sizes the implementation in principle permits arbitrary
> size mappings, but these require multiple identical leaf PTEs to be
> written, which isn't all that different from having to write multiple
> consecutive PTEs with increasing frame numbers. IMO that's therefore
> beneficial only on hardware where suitable TLBs exist; I'm unaware of
> such hardware.)
>
> Note that in principle 512G and 256T mappings could also be supported
> right away, but the freeing of page tables (to be introduced in
> subsequent patches) when replacing a sufficiently populated tree with a
> single huge page would need suitable preemption, which will require
> extra work.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Reviewed-by: Paul Durrant <paul@xxxxxxx>