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[PATCH 2/8] x86/boot: Collect AMD speculative features earlier during boot
- To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Wed, 26 Jan 2022 08:44:46 +0000
- Authentication-results: esa6.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Wed, 26 Jan 2022 08:45:15 +0000
- Ironport-data: A9a23:ZiU0k6yFeHWYO12CxWF6t+fjwSrEfRIJ4+MujC+fZmUNrF6WrkUDx zBKWGmCP/qIYWH1eYxxOt/l8U4H7MPTydNlGQE6pCAxQypGp/SeCIXCJC8cHc8zwu4v7q5Dx 59DAjUVBJlsFhcwnvopW1TYhSEUOZugH9IQM8aZfHAhLeNYYH1500g7wrRn2tcAbeWRWGthh /uj+6UzB3f9s9JEGjp8B3Wr8U4HUFza4Vv0j3RmDRx5lAa2e0o9VfrzEZqZPXrgKrS4K8bhL wr1IBNVyUuCl/slIovNfr8W6STmSJaKVeSFoiI+t6RPHnGuD8H9u0o2HKN0VKtZt9mGt9Yu9 4hOqrX3cCY0NajQveE6fiREGj4raMWq+JefSZS+mcmazkmAeHrw2fR+SkoxOOX0+M4uXzsIr 6ZBbmlQMFbT3Ipaw5riIgVoru0lINPmI8U0vXZ4wCuCJf0nXYrCU+PB4towMDIY2JoRRa6EP 5pxhTxHaDDDYjJJAA4uL60TzKD5qHD/cjNXpwfAzUYwyzeKl1EguFT3C/LKfvSaSMMTmVyXz krk1WnkBhARNPSE1CGItHmrg4fnjS79HY4fCrC83vprm0GIgHweDgUMUlm2quX/jVSxM++zM GRNpHBo9/JrshX2EJ+tBHVUvUJooDYaBOUNEPITrzis16HR/yOcIUU5UjdePYlOWNANeRQm0 VqAntXMDDNpsaGIRX/1yop4vQ9eKgBOczZcOHZsoR8tpoC6/dpt1k6nosNLTfbt5uAZDw0c1 NxjQMIWo7wIxfAG2Kyglbwsq2L9/8OZJuLZC+i+Y45E0u+bTNL0D2BLwQKChRqlEGp/ZgPQ1 JTjs5PGhN3i9bnXyESwrBwlRdlFHcqtPjzGmkJIFJI87Tmr8HPLVdkOvGonfxo3bppZKWCBj KrvVeV5vs470JyCNvcfXm5MI55ykfiI+SrNC5g4keaikrAuLVTarUmClGab3nz3kVhErE3ME czzTCpYNl5DUf4P5GPvH481iOZ3rghjmz+7bc2lnnyPjOrPDFbIGOxtGAbfMYgEAFas/V+9H yB3bZXakn2ykYTWP0HqzGLkBQladCdgXcGv9ZU/myzqClMOJVzNwsT5mdsJE7GJVYwL/gsR1 n3iCEJe1nTlgnjLdVeDZnx5Meu9Vpdjt3MreycrOA/wiXQkZI+u6oYZdoc2IuZ7pLAyk6YsQ qlXYdiED9ROVi/Dp2YXY67iodEwbx+snw+PYXaoOWBtY556SgXV0db4ZQ+zpjIWBy+6uJJm8 b2t3w/WW7QZQAFmAJqEYf6j1Qrp73MchPhzTw3DJdwKIBfg941jKirQiP4rIp5TdUWfl2XCj wvPWEUWv+jApYMx4eLlv6Hcotf7CfZ6E2pbA3LfseS8Ox7F8zfx2oRHSuuJI2zQDTum5KW4a OxJ5PjgK/lbzk1Suo9xHrs3n6Iz49zj++1Twgh+RSiZal2qDvVrI2Wc3NkJvapIn+cLtQyzU 0OJ299bJbTWZ5+1TA9PfFIoPraZyPUZujjO9vBkckz16Rh+8KeDTUgPbQKHjzZQLectPY4oq Qv7VBX6N+BrZsIWD+u7
- Ironport-hdrordr: A9a23:Fc++0qjx9an3AlvQHX9JtfF1l3BQXuIji2hC6mlwRA09TySZ// rBoB19726MtN9xYgBHpTnuAsm9qB/nmaKdpLNhWItKPzOW31dATrsSjrcKqgeIc0aVm9K1l5 0QF5SWYOeAdWSS5vya3ODXKbkdKaG8gcKVuds=
- Ironport-sdr: URKlWtNEx2vmIBHwWfZSPJeolnlGSKon28GiMVExP3rFLkBqi4vykSppC3LFyYm23Rsnas6ABP dskmSwvfJtDSIkdF1FokylUyo/t/Ne7RevIfgTdo2taSSWKR2hB/DU2btYLGdbaVsP0jA6oXP8 05gr4Ecsl8AV0zYs8SIur6jdi4GCokpTXfTeESRc/aL5kP+fRq4+dwED4MnWJz1EEeQucAofXx zSV9KupVFmB2TmERhWQhyW63w9TYYOEo0GaaMyIfCUCnQ8PzQRxqu3qWTbgvocK0kSZmUGpHuA lpQq7aDZK6Y5oyAh2n93Q7jP
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
All AMD IBRS-related features are in CPUID.0x80000008.ebx. Collect them in
early_cpu_init() so init_speculative_mitigations() can use them.
Rework the existing logic structure to fill in c->extended_cpuid_level and
separate out the ambiguous use of ebx in an otherwise 0x80000008-specific
logic block.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
CC: Wei Liu <wl@xxxxxxx>
---
xen/arch/x86/cpu/common.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 4a163afbfc7e..866f1a516447 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -348,9 +348,13 @@ void __init early_cpu_init(void)
}
eax = cpuid_eax(0x80000000);
- if ((eax >> 16) == 0x8000 && eax >= 0x80000008) {
- ebx = eax >= 0x8000001f ? cpuid_ebx(0x8000001f) : 0;
- eax = cpuid_eax(0x80000008);
+ if ((eax >> 16) == 0x8000)
+ c->extended_cpuid_level = eax;
+
+ if (c->extended_cpuid_level >= 0x80000008) {
+ cpuid(0x80000008, &eax,
+ &c->x86_capability[cpufeat_word(X86_FEATURE_CLZERO)],
+ &ecx, &edx);
paddr_bits = eax & 0xff;
if (paddr_bits > PADDR_BITS)
@@ -363,10 +367,11 @@ void __init early_cpu_init(void)
hap_paddr_bits = ((eax >> 16) & 0xff) ?: paddr_bits;
if (hap_paddr_bits > PADDR_BITS)
hap_paddr_bits = PADDR_BITS;
+ }
+ if (c->extended_cpuid_level >= 0x8000001f)
/* Account for SME's physical address space reduction. */
- paddr_bits -= (ebx >> 6) & 0x3f;
- }
+ paddr_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
park_offline_cpus = opt_mce;
--
2.11.0
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