[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v2 3/4] x86/APIC: skip unnecessary parts of __setup_APIC_LVTT()
In TDT mode there's no point writing TDCR or TMICT, while outside of that mode there's no need for the MFENCE. No change intended to overall functioning. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> --- v2: New. --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1059,24 +1059,25 @@ static void __setup_APIC_LVTT(unsigned i { unsigned int lvtt_value, tmp_value; - /* NB. Xen uses local APIC timer in one-shot mode. */ - lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR; - if ( tdt_enabled ) { - lvtt_value &= (~APIC_TIMER_MODE_MASK); - lvtt_value |= APIC_TIMER_MODE_TSC_DEADLINE; + lvtt_value = APIC_TIMER_MODE_TSC_DEADLINE | LOCAL_TIMER_VECTOR; + apic_write(APIC_LVTT, lvtt_value); + + /* + * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, + * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. + * According to Intel, MFENCE can do the serialization here. + */ + asm volatile( "mfence" : : : "memory" ); + + return; } + /* NB. Xen uses local APIC timer in one-shot mode. */ + lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR; apic_write(APIC_LVTT, lvtt_value); - /* - * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, - * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. - * According to Intel, MFENCE can do the serialization here. - */ - asm volatile( "mfence" : : : "memory" ); - tmp_value = apic_read(APIC_TDCR); apic_write(APIC_TDCR, tmp_value | APIC_TDR_DIV_1);
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