[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: HVM/PVH Balloon crash
On Tue, Sep 07, 2021 at 05:57:10PM +0200, Jan Beulich wrote: > On 07.09.2021 17:03, Elliott Mitchell wrote: > > Could be this system is in an > > intergenerational hole, and some spot in the PVH/HVM code makes an > > assumption of the presence of NPT guarantees presence of an operational > > IOMMU. Otherwise if there was some copy and paste while writing IOMMU > > code, some portion of the IOMMU code might be checking for presence of > > NPT instead of presence of IOMMU. > > This is all very speculative; I consider what you suspect not very likely, > but also not entirely impossible. This is not the least because for a > long time we've been running without shared page tables on AMD. > > I'm afraid without technical data and without knowing how to repro, I > don't see a way forward here. Downtimes are very expensive even for lower-end servers. Plus there is the issue the system wasn't meant for development and thus never had appropriate setup done. Experimentation with a system of similar age suggested another candidate. System has a conventional BIOS. Might some dependancies on the presence of UEFI snuck into the NPT code? -- (\___(\___(\______ --=> 8-) EHM <=-- ______/)___/)___/) \BS ( | ehem+sigmsg@xxxxxxx PGP 87145445 | ) / \_CS\ | _____ -O #include <stddisclaimer.h> O- _____ | / _/ 8A19\___\_|_/58D2 7E3D DDF4 7BA6 <-PGP-> 41D1 B375 37D0 8714\_|_/___/5445
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