[PATCH v2 1/2] x86/amd: split LFENCE dispatch serializing setup logic into helper

[Roger Pau Monne <roger.pau@xxxxxxxxxx>]

Split the logic to attempt to setup LFENCE to be dispatch serializing
on AMD into a helper, so it can be shared with Hygon.

No functional change intended.

Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
Changes since v1:
 - Fix typo in commit message.
---
 xen/arch/x86/cpu/amd.c   | 62 ++++++++++++++++++++++------------------
 xen/arch/x86/cpu/cpu.h   |  1 +
 xen/arch/x86/cpu/hygon.c | 27 +----------------
 3 files changed, 36 insertions(+), 54 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 8bc51bec10d..9c8dcd91eef 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -642,6 +642,38 @@ void early_init_amd(struct cpuinfo_x86 *c)
        ctxt_switch_levelling(NULL);
 }
 
+void amd_init_lfence(struct cpuinfo_x86 *c)
+{
+       uint64_t value;
+
+       /*
+        * Attempt to set lfence to be Dispatch Serialising.  This MSR almost
+        * certainly isn't virtualised (and Xen at least will leak the real
+        * value in but silently discard writes), as well as being per-core
+        * rather than per-thread, so do a full safe read/write/readback cycle
+        * in the worst case.
+        */
+       if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
+               /* Unable to read.  Assume the safer default. */
+               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+                           c->x86_capability);
+       else if (value & AMD64_DE_CFG_LFENCE_SERIALISE)
+               /* Already dispatch serialising. */
+               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
+                         c->x86_capability);
+       else if (wrmsr_safe(MSR_AMD64_DE_CFG,
+                           value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
+                rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
+                !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
+               /* Attempt to set failed.  Assume the safer default. */
+               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
+                           c->x86_capability);
+       else
+               /* Successfully enabled! */
+               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
+                         c->x86_capability);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
        u32 l, h;
@@ -686,37 +718,11 @@ static void init_amd(struct cpuinfo_x86 *c)
        if (c == &boot_cpu_data && !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS))
                setup_force_cpu_cap(X86_BUG_FPU_PTRS);
 
-       /*
-        * Attempt to set lfence to be Dispatch Serialising.  This MSR almost
-        * certainly isn't virtualised (and Xen at least will leak the real
-        * value in but silently discard writes), as well as being per-core
-        * rather than per-thread, so do a full safe read/write/readback cycle
-        * in the worst case.
-        */
        if (c->x86 == 0x0f || c->x86 == 0x11)
                /* Always dispatch serialising on this hardare. */
                __set_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability);
-       else /* Implicily "== 0x10 || >= 0x12" by being 64bit. */ {
-               if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
-                       /* Unable to read.  Assume the safer default. */
-                       __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
-                                   c->x86_capability);
-               else if (value & AMD64_DE_CFG_LFENCE_SERIALISE)
-                       /* Already dispatch serialising. */
-                       __set_bit(X86_FEATURE_LFENCE_DISPATCH,
-                                 c->x86_capability);
-               else if (wrmsr_safe(MSR_AMD64_DE_CFG,
-                                   value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
-                        rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
-                        !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
-                       /* Attempt to set failed.  Assume the safer default. */
-                       __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
-                                   c->x86_capability);
-               else
-                       /* Successfully enabled! */
-                       __set_bit(X86_FEATURE_LFENCE_DISPATCH,
-                                 c->x86_capability);
-       }
+       else /* Implicily "== 0x10 || >= 0x12" by being 64bit. */
+               amd_init_lfence(c);
 
        /*
         * If the user has explicitly chosen to disable Memory Disambiguation
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 1992596d1b2..1ac3b2867a0 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -20,3 +20,4 @@ extern bool detect_extended_topology(struct cpuinfo_x86 *c);
 
 void early_init_amd(struct cpuinfo_x86 *c);
 void amd_log_freq(const struct cpuinfo_x86 *c);
+void amd_init_lfence(struct cpuinfo_x86 *c);
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 46293f1f367..2272e1113f1 100644
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -32,32 +32,7 @@ static void init_hygon(struct cpuinfo_x86 *c)
 {
        unsigned long long value;
 
-       /*
-        * Attempt to set lfence to be Dispatch Serialising.  This MSR almost
-        * certainly isn't virtualised (and Xen at least will leak the real
-        * value in but silently discard writes), as well as being per-core
-        * rather than per-thread, so do a full safe read/write/readback cycle
-        * in the worst case.
-        */
-       if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
-               /* Unable to read.  Assume the safer default. */
-               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
-                           c->x86_capability);
-       else if (value & AMD64_DE_CFG_LFENCE_SERIALISE)
-               /* Already dispatch serialising. */
-               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
-                         c->x86_capability);
-       else if (wrmsr_safe(MSR_AMD64_DE_CFG,
-                           value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
-                rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
-                !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
-               /* Attempt to set failed.  Assume the safer default. */
-               __clear_bit(X86_FEATURE_LFENCE_DISPATCH,
-                           c->x86_capability);
-       else
-               /* Successfully enabled! */
-               __set_bit(X86_FEATURE_LFENCE_DISPATCH,
-                         c->x86_capability);
+       amd_init_lfence(c);
 
        /*
         * If the user has explicitly chosen to disable Memory Disambiguation
-- 
2.30.1