--- cpuid-xen-4.8.txt 2021-01-22 09:32:38.279999364 -0300 +++ cpuid-xen-4.14.txt 2021-01-22 09:24:58.776001456 -0300 @@ -18,9 +18,9 @@ brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true - VME: virtual-8086 mode enhancement = true + VME: virtual-8086 mode enhancement = false DE: debugging extensions = true - PSE: page size extensions = true + PSE: page size extensions = false TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true @@ -28,15 +28,15 @@ CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true - MTRR: memory type range registers = true - PTE global bit = true + MTRR: memory type range registers = false + PTE global bit = false MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true - PSE-36: page size extension = true + PSE-36: page size extension = false PSN: processor serial number = false CLFLUSH instruction = true - DS: debug store = true + DS: debug store = false ACPI: thermal monitor and clock ctrl = true MMX Technology = true FXSAVE/FXRSTOR = true @@ -44,41 +44,41 @@ SSE2 extensions = true SS: self snoop = true hyper-threading / multi-core supported = true - TM: therm. monitor = true + TM: therm. monitor = false IA64 = false - PBE: pending break event = true + PBE: pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true - DTES64: 64-bit debug store = true - MONITOR/MWAIT = true - CPL-qualified debug store = true - VMX: virtual machine extensions = true - SMX: safer mode extensions = true - Enhanced Intel SpeedStep Technology = true - TM2: thermal monitor 2 = true + DTES64: 64-bit debug store = false + MONITOR/MWAIT = false + CPL-qualified debug store = false + VMX: virtual machine extensions = false + SMX: safer mode extensions = false + Enhanced Intel SpeedStep Technology = false + TM2: thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = false FMA instruction = false CMPXCHG16B instruction = true - xTPR disable = true - PDCM: perfmon and debug = true - PCID: process context identifiers = true - DCA: direct cache access = true + xTPR disable = false + PDCM: perfmon and debug = false + PCID: process context identifiers = false + DCA: direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true x2APIC: extended xAPIC support = true MOVBE instruction = false POPCNT instruction = true - time stamp counter deadline = true + time stamp counter deadline = false AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true - hypervisor guest status = false + hypervisor guest status = true cache and TLB information (2): 0x63: data TLB: 2M/4M pages, 4-way, 32 entries data TLB: 1G pages, 4-way, 4 entries @@ -155,25 +155,25 @@ number of sets (s) = 24576 (size synth) = 31457280 (30 MB) MONITOR/MWAIT (5): - smallest monitor-line size (bytes) = 0x40 (64) - largest monitor-line size (bytes) = 0x40 (64) - enum of Monitor-MWAIT exts supported = true - supports intrs as break-event for MWAIT = true + smallest monitor-line size (bytes) = 0x0 (0) + largest monitor-line size (bytes) = 0x0 (0) + enum of Monitor-MWAIT exts supported = false + supports intrs as break-event for MWAIT = false number of C0 sub C-states using MWAIT = 0x0 (0) - number of C1 sub C-states using MWAIT = 0x2 (2) - number of C2 sub C-states using MWAIT = 0x1 (1) - number of C3 sub C-states using MWAIT = 0x1 (1) + number of C1 sub C-states using MWAIT = 0x0 (0) + number of C2 sub C-states using MWAIT = 0x0 (0) + number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): - digital thermometer = true + digital thermometer = false Intel Turbo Boost Technology = false - ARAT always running APIC timer = true - PLN power limit notification = true - ECMD extended clock modulation duty = true - PTM package thermal management = true + ARAT always running APIC timer = false + PLN power limit notification = false + ECMD extended clock modulation duty = false + PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false @@ -188,10 +188,10 @@ HW_FEEDBACK MSRs supported = false ignoring idle logical processor HWP req = false enhanced hardware feedback interface = false - digital thermometer thresholds = 0x2 (2) - hardware coordination feedback = true + digital thermometer thresholds = 0x0 (0) + hardware coordination feedback = false ACNT2 available = false - performance-energy bias capability = true + performance-energy bias capability = false number of enh hardware feedback classes = 0x0 (0) performance capability reporting = false energy efficiency capability reporting = false @@ -205,7 +205,7 @@ HLE hardware lock elision = false AVX2: advanced vector extensions 2 = false FDP_EXCPTN_ONLY = false - SMEP supervisor mode exec protection = true + SMEP supervisor mode exec protection = false BMI2 instructions = false enhanced REP MOVSB/STOSB = true INVPCID instruction = false @@ -279,12 +279,12 @@ IA32_CORE_CAPABILITIES MSR = false SSBD: speculative store bypass disable = false Direct Cache Access Parameters (9): - PLATFORM_DCA_CAP MSR bits = 1 + PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa): - version ID = 0x3 (3) - number of counters per logical processor = 0x4 (4) - bit width of counter = 0x30 (48) - length of EBX bit vector = 0x7 (7) + version ID = 0x0 (0) + number of counters per logical processor = 0x0 (0) + bit width of counter = 0x0 (0) + length of EBX bit vector = 0x0 (0) core cycle event not available = false instruction retired event not available = false reference cycles event not available = false @@ -324,21 +324,9 @@ fixed counter 29 supported = false fixed counter 30 supported = false fixed counter 31 supported = false - number of fixed counters = 0x3 (3) - bit width of fixed counters = 0x30 (48) + number of fixed counters = 0x0 (0) + bit width of fixed counters = 0x0 (0) anythread deprecation = false - x2APIC features / processor topology (0xb): - extended APIC ID = 0 - --- level 0 --- - level number = 0x0 (0) - level type = thread (1) - bit width of level = 0x1 (1) - number of logical processors at level = 0x2 (2) - --- level 1 --- - level number = 0x1 (1) - level type = core (2) - bit width of level = 0x5 (5) - number of logical processors at level = 0x18 (24) XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x00000007 XCR0 upper 32 bits valid bit field mask = 0x00000000 @@ -377,10 +365,40 @@ supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false + hypervisor_id = "XenVMMXenVMM" + hypervisor version (0x40000001/eax): + version = 4.14 + hypervisor features (0x40000002): + number of hypercall-transfer pages = 0x1 (1) + MSR base address = 0x40000000 + MMU_PT_UPDATE_PRESERVE_AD supported = true + hypervisor time features (0x40000003/00): + vtsc = false + host tsc is safe = false + boot cpu has RDTSCP = true + tsc mode = 0x0 (0) + tsc frequency (kHz) = 0 + incarnation = 0x0 (0) + hypervisor time scale & offset (0x40000003/01): + vtsc offset = 0x0 (0) + vtsc mul_frac = 0x0 (0) + vtsc shift = 0x0 (0) + hypervisor time physical cpu frequency (0x40000003/02): + cpu frequency (kHZ) = 2494348 + HVM-specific parameters (0x40000004): + virtualized APIC registers = false + virtualized x2APIC accesses = false + IOMMU mappings for other domain memory = false + vcpu id is valid = false + domain id is valid = false + vcpu id = 0x0 (0) + domain id = 0x0 (0) + PV-specific parameters (0x40000005): + maximum machine address width = 0x24 (36) extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true - 1-GB large page support = true + 1-GB large page support = false RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): @@ -476,9 +494,9 @@ performance time-stamp counter size = 0x0 (0) Feature Extended Size (0x80000008/edx): RDPRU instruction max input support = 0x0 (0) - (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2) - (multi-processing method) = Intel leaf 0xb - (APIC widths synth): CORE_width=5 SMT_width=1 + (multi-processing synth) = multi-core (c=16), hyper-threaded (t=2) + (multi-processing method) = Intel leaf 1/4 + (APIC widths synth): CORE_width=4 SMT_width=1 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm