Re: [PATCH v3 07/15] x86/alternative: support "not feature" and ALTERNATIVE_TERNARY

[Jürgen Groß <jgross@xxxxxxxx>]

On 07.01.21 20:08, Borislav Petkov wrote:
> On Thu, Dec 17, 2020 at 10:31:25AM +0100, Juergen Gross wrote:
> > Instead of only supporting to modify instructions when a specific
> > feature is set, support doing so for the case a feature is not set.
> >
> > As today a feature is specified using a 16 bit quantity and the highest
> > feature number in use is around 600, using a negated feature number for
> > specifying the inverted case seems to be appropriate.
> >
> >    ALTERNATIVE "default_instr", "patched_instr", ~FEATURE_NR
> >
> > will start with "default_instr" and patch that with "patched_instr" in
> > case FEATURE_NR is not set.
> >
> > Using that add ALTERNATIVE_TERNARY:
> >
> >    ALTERNATIVE_TERNARY "default_instr", FEATURE_NR,
> >                        "feature_on_instr", "feature_off_instr"
> >
> > which will start with "default_instr" and at patch time will, depending
> > on FEATURE_NR being set or not, patch that with either
> > "feature_on_instr" or "feature_off_instr".
> How about an even simpler one (only build-tested):
>
> ---
> diff --git a/arch/x86/include/asm/alternative-asm.h 
> b/arch/x86/include/asm/alternative-asm.h
> index 464034db299f..d52b423d3cab 100644
> --- a/arch/x86/include/asm/alternative-asm.h
> +++ b/arch/x86/include/asm/alternative-asm.h
> @@ -109,6 +109,9 @@
>         .popsection
>   .endm
>   
> +#define ALTERNATIVE_TERNARY(oldinstr, feature, newinstr1, newinstr2)	\
> +       ALTERNATIVE_2 oldinstr, newinstr1, feature, newinstr2, 
> X86_FEATURE_TERNARY
> +
>   #endif  /*  __ASSEMBLY__  */
>   
>   #endif /* _ASM_X86_ALTERNATIVE_ASM_H */
> diff --git a/arch/x86/include/asm/alternative.h 
> b/arch/x86/include/asm/alternative.h
> index 13adca37c99a..f170cbe89539 100644
> --- a/arch/x86/include/asm/alternative.h
> +++ b/arch/x86/include/asm/alternative.h
> @@ -175,6 +175,9 @@ static inline int alternatives_text_reserved(void *start, 
> void *end)
>         ALTINSTR_REPLACEMENT(newinstr2, feature2, 2)                    \
>         ".popsection\n"
>   
> +#define ALTERNATIVE_TERNARY(oldinstr, feature, newinstr1, newinstr2)	\
> +       ALTERNATIVE_2(oldinstr, newinstr1, feature, newinstr2, 
> X86_FEATURE_TERNARY)
> +
>   #define ALTERNATIVE_3(oldinsn, newinsn1, feat1, newinsn2, feat2, newinsn3, 
> feat3) \
>         OLDINSTR_3(oldinsn, 1, 2, 3)                                            
> \
>         ".pushsection .altinstructions,\"a\"\n"                                 
>     \
> @@ -206,6 +209,9 @@ static inline int alternatives_text_reserved(void *start, 
> void *end)
>   #define alternative_2(oldinstr, newinstr1, feature1, newinstr2, feature2) \
>         asm_inline volatile(ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, 
> feature2) ::: "memory")
>   
> +#define alternative_ternary(oldinstr, feature, newinstr1, newinstr2)	\
> +       asm_inline volatile(ALTERNATIVE_TERNARY(oldinstr, feature, newinstr1, newinstr2) 
> ::: "memory")
> +
>   /*
>    * Alternative inline assembly with input.
>    *
> diff --git a/arch/x86/include/asm/cpufeatures.h 
> b/arch/x86/include/asm/cpufeatures.h
> index 84b887825f12..cc634db0b91f 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -108,7 +108,7 @@
>   #define X86_FEATURE_EXTD_APICID               ( 3*32+26) /* Extended APICID 
> (8 bits) */
>   #define X86_FEATURE_AMD_DCM           ( 3*32+27) /* AMD multi-node processor 
> */
>   #define X86_FEATURE_APERFMPERF                ( 3*32+28) /* P-State hardware 
> coordination feedback capability (APERF/MPERF MSRs) */
> -/* free                                        ( 3*32+29) */
> +#define X86_FEATURE_TERNARY            ( 3*32+29) /* "" Synthetic bit for 
> ALTERNATIVE_TERNARY() */
In fact this should rather be named "X86_FEATURE_TRUE", as this is its
semantics.

And I think I can define it to the value 0xffff instead of using a
"real" bit for it.


Juergen

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