[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] x86/dpci: remove the dpci EOI timer


  • To: Jan Beulich <jbeulich@xxxxxxxx>
  • From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Date: Thu, 14 Jan 2021 18:22:59 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NagT/LfuuWX0TA+hs0uPhgrQSmhXEMoKgSnwZJLwOes=; b=ZT/k5Oh7TeK+bowHY5rwrpnJAXvW6gDoRSYUVTFVHUNJlxNw6WPKmPwNVl4GsIPN+MHez/IrqpHV7GC7M5AK9lu1k9x9QHRQfSSUd+STlw7tjcsPKIGk4RjyiPT3krQHk8mSu81om6FiJldZsHKJD88/whIPhRFnQghRHnvAF32u4ZiK8SoeTf9lAr+0Frxp/ChxZfe5A+hFN8Px9f+Q4SVmdEyNxD/eahsWqNGpNJq+rxuqK65ijn3/44rfYUr1YnmhhFju2/EoBAZaz/lmwMZTeuIJ+f1n0AcJEP2YKEBoG+WkL5MLV6FKPNjZMI35Am2uu9w5inKXvzQ4HHfFsw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UwVXAmBunClczPtzl5+lF5On9H6WhVICB5VfulbYhW8WeC5bP4L1vjhAruJfmNdUSr/E2wVs6mT2XSC0vZCFUK+5L1e1N34TZ1OjIimfXjFot5d0JsmVx0h0nKi0Aat4f2BF67aaMreixY34i7wVRzl7K4O/OzTiBNkROstz5yhHqEzkhFDvJxu696xI/Ifi4FY66mqf+mpXMU5bDC0B5TySwqAH68Vu3WkWCPE+8IbJ0IDPCLknWQUl7LYGpDKJVBKYHNgjmkJR2xu2Zn29+4qrga9t+ubu53qqdxz2f1xVj3c0RxERABv7Q735IIhvjTYFy0icqElYiB3hzikXMA==
  • Authentication-results: esa1.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Paul Durrant <paul@xxxxxxx>, "Cooper, Andrew" <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, "Tian, Kevin" <kevin.tian@xxxxxxxxx>
  • Delivery-date: Thu, 14 Jan 2021 17:23:10 +0000
  • Ironport-sdr: ypm2F9ZJpOL7q4iAcl81HA6xP7iN13JIUMIjbqiU/Ngx3vxUB8xoRlO0MIQKPgkJruu87sY1Z0 i+B3+RnDbogoyd3hGSBtYyizLxL2/XVgRs+Dfsjq46Dv29v3T25pBknguyq0/HZT2vC9pTkxq9 yNOSQhtTafi8Vqp+knNNBPubRhXhkqsC0FU6kFvu5wGqqFfXS6N+CNtpYYLNVFwwLQVhcscIOv pzB9X5r/WxVI9/2rSt18QwbdEnU07vu8TaaLBfv3TpPKOF5JMk0lOhtfZeOWLAb6TD9jGsXfYZ cbI=
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Thu, Jan 14, 2021 at 02:30:15PM +0100, Jan Beulich wrote:
> On 14.01.2021 13:54, Roger Pau Monné wrote:
> > On Thu, Jan 14, 2021 at 12:48:59PM +0100, Jan Beulich wrote:
> >> On 13.01.2021 14:11, Roger Pau Monné wrote:
> >>> On Wed, Jan 13, 2021 at 06:21:03AM +0000, Tian, Kevin wrote:
> >>>>> From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
> >>>>> As with previous patches, I'm having a hard time figuring out why this
> >>>>> was required in the first place. I see no reason for Xen to be
> >>>>> deasserting the guest virtual line. There's a comment:
> >>>>>
> >>>>> /*
> >>>>>  * Set a timer to see if the guest can finish the interrupt or not. For
> >>>>>  * example, the guest OS may unmask the PIC during boot, before the
> >>>>>  * guest driver is loaded. hvm_pci_intx_assert() may succeed, but the
> >>>>>  * guest will never deal with the irq, then the physical interrupt line
> >>>>>  * will never be deasserted.
> >>>>>  */
> >>>>>
> >>>>> Did this happen because the device was passed through in a bogus state
> >>>>> where it would generate interrupts without the guest requesting
> >>>>
> >>>> It could be a case where two devices share the same interrupt line and
> >>>> are assigned to different domains. In this case, the interrupt activity 
> >>>> of 
> >>>> two devices interfere with each other.
> >>>
> >>> This would also seem to be problematic if the device decides to use
> >>> MSI instead of INTx, but due to the shared nature of the INTx line we
> >>> would continue to inject INTx (generated from another device not
> >>> passed through to the guest) to the guest even if the device has
> >>> switched to MSI.
> >>
> >> I'm having trouble with this: How does the INTx line matter when
> >> a device is using MSI? I don't see why we should inject INTx when
> >> the guest has configured a device for MSI; if we do, this would
> >> indeed look like a bug (but aiui we bind either the MSI IRQ or
> >> the pin based one, but not both).
> > 
> > If the IRQ is shared between multiple devices Xen could continue to
> > receive interrupts on that IRQ, and thus inject them to the guest?
> > Even if the device passed through to that specific guest has switched
> > to use MSI.
> > 
> > Maybe I'm missing something, but I don't see QEMU removing the INTx
> > PIRQ binding when MSI(-X) is enabled for a guest device passed
> > through.
> 
> This would then match my "would indeed look like a bug". I don't see
> why this mapping would need keeping once MSI is in use. (In fact it
> probably shouldn't be the act of enabling MSI where this gets
> removed, but the setting of PCI_COMMAND_INTX_DISABLE by the guest.)

We would also need to assert that no other passthrough device on the
guest is using that same irq bounding, or else we would wedge
interrupts for that other device.

Thanks, Roger.



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.