[PATCH] x86/Intel: insert Tiger Lake model numbers

[Jan Beulich <jbeulich@xxxxxxxx>]

Both match prior generation processors as far as LBR and C-state MSRs
go (SDM rev 073). The if_pschange_mc erratum, according to the spec
update, is not applicable.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -183,6 +183,9 @@ static void do_get_hw_residencies(void *
     /* Ice Lake */
     case 0x7D:
     case 0x7E:
+    /* Tiger Lake */
+    case 0x8C:
+    case 0x8D:
     /* Kaby Lake */
     case 0x8E:
     case 0x9E:
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2436,6 +2436,12 @@ static bool __init has_if_pschange_mc(vo
         return true;
 
         /*
+         * Newer Core processors are not vulnerable.
+         */
+    case 0x8c: /* Tiger Lake */
+    case 0x8d: /* Tiger Lake */
+
+        /*
          * Atom processors are not vulnerable.
          */
     case 0x1c: /* Pineview */
@@ -2776,6 +2782,8 @@ static const struct lbr_info *last_branc
         case 0x7a:
         /* Ice Lake */
         case 0x7d: case 0x7e:
+        /* Tiger Lake */
+        case 0x8c: case 0x8d:
         /* Tremont */
         case 0x86:
         /* Kaby Lake */