Re: [PATCH 00/10] x86emul: full coverage mem access / write testing

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 03/08/2020 15:47, Jan Beulich wrote:
> ... and a few fixes resulting from this work. This completes what
> was started for legacy encoded GPR insns in a rush before 4.14.
>
> There's one thing I'm still planning on top of both this and the
> EVEX-disp8 checking: For all encodings we produce via general
> logic (and in particular without involvement of any assembler) I'd
> like to add a kind of logging mechanism, the output of which could
> be fed to gas and then some disassembler, to allow verification
> that the produced encodings are actually valid ones. See e.g. the
> first patch here or commit 5f55389d6960 - the problems addressed
> there could have been caught earlier if the generated encodings
> could be easily disassembled. What's not clear to me here is
> whether this is deemed generally useful, or whether I should make
> this a private addition of mine.
>
> 01: adjustments to mem access / write logic testing
> 02: extend decoding / mem access testing to FPU insns
> 03: extend decoding / mem access testing to MMX / SSE insns
> 04: extend decoding / mem access testing to VEX-encoded insns
> 05: extend decoding / mem access testing to XOP-encoded insns
> 06: AVX512{F,BW} down conversion moves are memory writes
> 07: AVX512F scatter insns are memory writes
> 08: AVX512PF insns aren't memory accesses
> 09: extend decoding / mem access testing to EVEX-encoded insns
> 10: correct AVX512_BF16 insn names in EVEX Disp8 test

Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Ideally with the commit message for patch 3 adjusted.